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參數(shù)資料
| 型號： | IDT5V49EE902NLGI |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 15/33頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN PLL 500MHZ 32VFQFPN |
| 標準包裝： | 490 |
| 類型： | * |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS，LVTTL，晶體 |
| 輸出： | HCSL，LVCMOS，LVDS，LVPECL，LVTTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:7 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 500MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-VFQFPN（5x5） |
| 包裝： | 托盤 |
| 其它名稱： | 800-2582 |
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IDT5V49EE902
EEPROM PROGRAMMABLE CLOCK GENERATOR
CLOCK SYNTHESIZER
IDT EEPROM PROGRAMMABLE CLOCK GENERATOR
22
IDT5V49EE902
REV P 092412
Spread Spectrum Generation Specifications
Test Circuits and Conditions
Test Circuits for DC Outputs
t8
Output Skew
Skew between output to output on the same
bank
75
ps
t9 4
Lock Time
PLL lock time from power-up
10
20
ms
t10 5
Lock Time
PLL lock time from shutdown mode
2
ms
1.Practical lower frequency is determined by loop filter settings.
2.A slew rate of 2.75V/ns or greater should be selected for output frequencies of 100MHz or higher.
3.Jitter measured with clock outputs of 27 MHz, 48 MHz, 24.576 MHz, 74.25 MHz and 25 MHz.
4.Includes loading the configuration bits from EEPROM to PLL registers. It does not include EEPROM programming/write time.
5.Actual PLL lock time depends on the loop configuration.
Symbol
Parameter
Description
Min
Typ
Max
Unit
fIN
1
1.Practical lower frequency is determined by loop filter settings.
Input Frequency Input Frequency Limit
1
400
MHz
fMOD
Mod Frequency
Modulation Frequency
33
120
kHz
fSPREAD Spread Value
Amount of Spread Value (programmable) - Down Spread
-0.5
-4.0
%fOUT
Amount of Spread Value (programmable) - Center Spread
±0.25
±2.0
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Units
OUTx
VDD
CLKOUT
GND
CL
0.1F
VDDOx
0.1F
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