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參數(shù)資料
| 型號： | IDT5V49EE902NLGI |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 28/33頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN PLL 500MHZ 32VFQFPN |
| 標準包裝： | 490 |
| 類型： | * |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS，LVTTL，晶體 |
| 輸出： | HCSL，LVCMOS，LVDS，LVPECL，LVTTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:7 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 500MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 32-VFQFPN（5x5） |
| 包裝： | 托盤 |
| 其它名稱： | 800-2582 |
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IDT5V49EE902
EEPROM PROGRAMMABLE CLOCK GENERATOR
CLOCK SYNTHESIZER
IDT EEPROM PROGRAMMABLE CLOCK GENERATOR
4
IDT5V49EE902
REV P 092412
OUT1
7
O
Adjustable1
Configurable clock output 1. Single-ended or differential
when combined with OUT2. Output levels controlled by
VDDO1.
OUT2
8
O
Adjustable1
Configurable clock output 2. Single-ended or differential
when combined with OUT1. Output levels controlled by
VDDO1.
OUT3
24
O
Adjustable1
Configurable clock output 3. Single-ended or differential
when combined with OUT6. Output levels controlled by
VDDO3.
OUT4
10
O
Adjustable1,2
Configurable clock output 4. Single-ended or differential
when combined with OUT4b. Output levels controlled by
VDDO4.
OUT4b
11
O
Adjustable1,2
Configurable clock output 4b. Single-ended or differential
when combined with OUT4. Output levels controlled by
VDDO4.
OUT5
14
O
Adjustable1,2
Configurable clock output 5. Single-ended or differential
when combined with OUT5b. Output levels controlled by
VDDO5.
OUT5b
15
O
Adjustable1,2
Configurable clock output 5b. Single-ended or differential
when combined with OUT5. Output levels controlled by
VDDO5.
OUT6
23
O
Adjustable1
Configurable clock output 6. Single-ended or differential
when combined with OUT3. Output levels controlled by
VDDO3.
VDD
1,4, 21,
32
Power
Device power supply. Connect to 3.3V.
VDDx
4
Power
Crystal oscillator power supply. Connect to 3.3V through
5
Ω resistor. Use filtered analog power supply if available.
AVDD
21
Power
Device analog power supply. Connect to 3.3V. Use
filtered analog power supply if available.
VDDO1
9
Power
Device power supply. Connect to 1.8 to 3.3V. Sets output
voltage levels for OUT1 and OUT2.
VDDO3
25
Power
Device power supply. Connect to 1.8 to 3.3V. Sets output
voltage levels for OUT3 and OUT6.
VDDO4
12
Power
Device power supply. Connect to 1.8 to 3.3V. Sets output
voltage levels for OUT4 and OUT4b.
VDDO5
16
Power
Device power supply. Connect to 1.8 to 3.3V. Sets output
voltage levels for OUT5 and OUT5b.
GND
6, 13,
17, 22,
31,PAD
Power
Connect to Ground.
1.Outputs are user programmable to drive single-ended 3.3-V LVTTL, or differential LVDS, LVPECL or HCSL interface levels
2. When only an individual single-ended clock output is required, tie OUT# and OUT#b together.
3. Analog power plane should be isolated from a 3.3V power plane through a ferrite bead.
4. Each power pin should have a dedicated 0.01F de-coupling capacitor. Digital VDDs may be tied together.
5. Unused clock inputs (REFIN or CLKIN) must be pulled high or low - they cannot be left floating. If the crystal oscillator is not used, XOUT must be left floating.
Pin Name
NL32
Pin#
I/O
Pin Type
Pin Description
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