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參數(shù)資料
| 型號： | IDT5T9010BBGI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 5T SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA144 |
| 封裝： | LEAD FREE, PLASTIC, BGA-144 |
| 文件頁數(shù)： | 2/23頁 |
| 文件大?。?/td> | 168K |
| 代理商： | IDT5T9010BBGI |
10
INDUSTRIALTEMPERATURERANGE
IDT5T9010
2.5V PROGRAMMABLE SKEW PLL CLOCK DRIVER TERACLOCK
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR eHSTL
Symbol
Parameter
Value
Units
VDIF
Input Signal Swing(1)
1V
VX
Differential Input Signal Crossing Point(2)
900
mV
VTHI
Input Timing Measurement Reference Level(3)
Crossing Point
V
tR, tF
Input Signal Edge Rate(4)
1
V/ns
NOTES:
1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC)
specification under actual use conditions.
2. A 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under
actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 1V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
NOTES:
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.
2. The termination resistors are excluded from these measurements.
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
4. FS = HIGH.
POWER SUPPLY CHARACTERISTICS FOR eHSTL OUTPUTS(1)
Symbol
Parameter
Test Conditions(2)
Typ.
Max
Unit
IDDQ
Quiescent VDD Power Supply Current(3)
VDDQ = Max., REF = LOW,
PD = HIGH, nSOE = LOW,
100
150
mA
PLL_EN = HIGH, DS[1:0] = MM, nF[2:0] = LHH,
FBF[2:0] = LHH, Outputs enabled, All outputs unloaded
IDDQQ
Quiescent VDDQ Power Supply Current(3)
VDDQ = Max., REF = LOW,
PD = HIGH, nSOE = LOW,
1.8
50
μA
PLL_EN = HIGH, DS[1:0] = MM, nF[2:0] = LHH,
FBF[2:0] = LHH, Outputs enabled, All outputs unloaded
IDDPD
Power Down Current
VDD = Max.,
PD = LOW, nSOE = LOW, PLL_EN = HIGH
1.7
5
mA
IDDD
Dynamic VDD Power Supply
VDD = Max., VDDQ = Max., CL = 0pF
19
30
μA/MHz
CurrentperOutput
IDDDQ
Dynamic VDDQ Power Supply
VDD = Max., VDDQ = Max., CL = 0pF
17
30
CurrentperOutput
ITOT
Total Power VDD Supply Current(4)
VDDQ = 1.8V, FVCO = 100MHz, CL = 15pF
115
170
mA
VDDQ = 1.8V, FVCO = 250MHz, CL = 15pF
150
225
ITOTQ
Total Power VDDQ Supply Current(4)
VDDQ = 1.8V, FVCO = 100MHz, CL = 15pF
45
70
mA
VDDQ = 1.8V, FVCO = 250MHz, CL = 15pF
100
150
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