參數(shù)資料
型號(hào): IDT5T907PAGI
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘及定時(shí)
英文描述: 5T SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
封裝: GREEN, TSSOP-48
文件頁(yè)數(shù): 1/17頁(yè)
文件大?。?/td> 111K
代理商: IDT5T907PAGI
INDUSTRIALTEMPERATURERANGE
IDT5T907
2.5VSINGLEDATARATE1:10CLOCKBUFFERTERABUFFER
1
FEBRUARY 2003
IDT5T907
INDUSTRIAL TEMPERATURE RANGE
2.5V SINGLE DATA RATE
1:10 CLOCK BUFFER
TERABUFFER
DESCRIPTION:
The IDT5T907 2.5V single data rate (SDR) clock buffer is a user-selectable
single-ended or differential input to ten single-ended outputs buffer built on
advancedmetalCMOStechnology. TheSDRclockbufferfanoutfromasingle
or differential input to ten single-ended outputs reduces the loading on the
preceding driver and provides an efficient clock distribution network. The
IDT5T907 can act as a translator from a differential HSTL, eHSTL, 1.8V/2.5V
LVTTL, LVEPECL, or single-ended 1.8V/2.5V LVTTL input to HSTL, eHSTL,
1.8V/2.5V LVTTL outputs. Selectable interface is controlled by 3-level input
signals that may be hard-wired to appropriate high-mid-low levels.
The IDT5T907 has two output banks that can be asynchronously enabled/
disabled. Multiple power and grounds reduce noise.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2003 Integrated Device Technology, Inc.
DSC-5899/22
FEATURES:
Guaranteed Low Skew < 25ps (max)
Very low duty cycle distortion
High speed propagation delay < 2.5ns. (max)
Up to 250MHz operation
Very low CMOS power levels
1.5V VDDQ for HSTL interface
Hot insertable and over-voltage tolerant inputs
3-level inputs for selectable interface
Selectable HSTL, eHSTL, 1.8V / 2.5V LVTTL, or LVEPECL input
interface
Selectable differential or single-ended inputs and ten single-
ended outputs
2.5V VDD
Available in TSSOP package
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS:
Clock and signal distribution
TxS
GL
G1
RxS
A
A/VREF
G2
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
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