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參數(shù)資料
| 型號： | IDT5T9010BBGI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 5T SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA144 |
| 封裝： | LEAD FREE, PLASTIC, BGA-144 |
| 文件頁數(shù)： | 18/23頁 |
| 文件大?。?/td> | 168K |
| 代理商： | IDT5T9010BBGI |
4
INDUSTRIALTEMPERATURERANGE
IDT5T9010
2.5V PROGRAMMABLE SKEW PLL CLOCK DRIVER TERACLOCK
PIN DESCRIPTION, CONTINUED
Symbol
I/O
Type
Description
REF_SEL
I
LVTTL(1)
Reference clock select. When LOW, selects REF0 and
REF0/VREF0. When HIGH, selects REF1 and REF1/VREF1.
nsOE
I
LVTTL(1)
Synchronous output enable. When
nsOEisHIGH,nQ[1:0]aresynchronouslystopped. OMODEselectswhethertheoutputsaregated
LOW/HIGH or tri-stated. When OMODE is HIGH, PE determines the level at which the outputs stop. When PE is LOW/HIGH, the
nQ[1:0] is stopped in a HIGH/LOW state. When OMODE is LOW, the outputs are tri-stated. Set
nsOE LOW for normal operation.
QFB
O
Adjustable(2)
Feedbackclockoutput
QFB
O
Adjustable(2)
Complementary feedback clock output
nQ[1:0]
O
Adjustable(2)
Five banks of two outputs
RxS
I
3-Level(3)
Selects single-ended 2.5V LVTTL (HIGH), 1.8V LVTTL (MID) REF clock input or differential (LOW) REF clock input
TxS
I
3-Level(3)
Sets the drive strength of the output drivers and feedback inputs to be 2.5V LVTTL (HIGH), 1.8V LVTTL (MID) or HSTL/eHSTL (LOW)
compatible. Used in conjuction with VDDQ to set the interface levels.
PE
I
LVTTL(1)
Selectablepositiveornegativeedgecontrol. WhenLOW/HIGHtheoutputsaresynchronizedwiththenegative/positiveedgeofthereference
clock (has internal pull-up).
nF[2:0]
I
3-Level(3)
3-level inputs for selecting 1 to 18 skew taps or frequency functions (See Control Summary table)
FBF[2:0]
I
3-Level(3)
3-level inputs for selecting 1 to 18 skew taps or frequency functions (See Control Summary table)
FS
I
LVTTL(1)
Selects appropriate oscillator circuit based on anticipated frequency range (See Programmable Skew Range)
DS[1:0]
I
3-Level(3)
3-level inputs for feedback input divider selection (See Divide Selection table)
PLL_EN
I
LVTTL(1)
PLL enable/disable control. Set LOW for normal operation. When
PLL_ENisHIGH,thePLLisdisabledandREF[1:0]goestoalloutputs.
PD
I
LVTTL(1)
Power down control. When
PDisLOW,theinputsaredisabledandinternalswitchingisstopped. OMODEselectswhethertheoutputs
are gated LOW/HIGH or tri-stated. When OMODE is HIGH, PE determines the level at which the outputs stop. When PE is LOW/
HIGH, the nQ[1:0] and QFB are stopped in a HIGH/LOW state, while the
QFB is stopped in a LOW/HIGH state. When OMODE is
LOW, the outputs are tri-stated. Set
PD HIGH for normal operation.
LOCK
O
LVTTL
PLL lock indication signal. HIGH indicates lock. LOW indicates that the PLL is not locked and outputs may not be synchronized to the
inputs. (For more information on application specific use of the LOCK pin, please see AN237.)
OMODE
I
LVTTL(1)
Output disable control. Determines the outputs' disable state. Used in conjunction with
nsOEandPD. (SeeOutputEnable/Disableand
Powerdown tables.)
VDDQ
PWR
Power supply for output buffers. When using 2.5V LVTTL, VDDQ should be connected to VDD.
VDD
PWR
Power supply for phase locked loop, lock output, inputs, and other internal circuitry
GND
PWR
Ground
NOTES:
1. Pins listed as LVTTL inputs will accept 2.5V signals under all conditions. If the output is operating at 1.8V or 1.5V, the LVTTL inputs will accept the 1.8V LVTTL signals as
well.
2. Outputs are user selectable to drive 2.5V, 1.8V LVTTL, eHSTL, or HSTL interface levels when used with the appropriate VDDQ voltage.
3. 3-level inputs are static inputs and must be tied to VDD or GND or left floating. These inputs are not hot-insertable or over voltage tolerant.
NOTE:
1. PE determines the level at which the outputs stop. When PE is LOW/HIGH, the
nQ[1:0] is stopped in a HIGH/LOW state.
OUTPUTENABLE/DISABLE
nsOE
OMODE
Output
L
X
NormalOperation
H
L
Tri-State
H
Gated(1)
NOTE:
1. PE determines the level at which the outputs stop. When PE is LOW/HIGH, the
nQ[1:0] and QFB are stopped in a HIGH/LOW state, while the
QFB is stopped in a
LOW/HIGH state.
POWERDOWN
PD
OMODE
Output
H
X
NormalOperation
L
Tri-State
L
H
Gated(1)
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