參數(shù)資料
型號(hào): ICY7C1362C-166BZI
廠(chǎng)商: CYPRESS SEMICONDUCTOR CORP
元件分類(lèi): DRAM
英文描述: 9-Mbit (256K x 36/512K x 18) Pipelined SRAM
中文描述: 512K X 18 CACHE SRAM, 3.5 ns, PBGA165
封裝: 13 X 15 MM, 1.40 HEIGHT, FBGA-165
文件頁(yè)數(shù): 31/31頁(yè)
文件大?。?/td> 432K
代理商: ICY7C1362C-166BZI
PRELIMINARY
CY7C1360C
CY7C1362C
Document #: 38-05540 Rev. *C
Page 31 of 31
Document History Page
Document Title: CY7C1360C/CY7C1362C 9-Mbit (256K x 36/512K x 18) Pipelined SRAM
Document Number: 38-05540
Orig. of
Change
**
241690
See ECN
RKF
*A
278130
See ECN
RKF
REV.
ECN NO.
Issue Date
Description of Change
New data sheet
Changed Boundary Scan order to match the B rev of these devices.
Changed TQFP pkg to Lead-free TQFP in Ordering Information section
Added comment of Lead-free BG and BZ packages availability
Changed ISB1 and ISB3 from DC Characteristics table as follows:
ISB1: 225 MHz -> 130 mA, 200 MHz -> 120 mA, 167 MHz -> 110 mA
ISB3: 225 MHz -> 120 mA, 200 MHz -> 110 mA, 167 MHz -> 100 mA
Changed IDDZZ to 50mA.
Added BG and BZ pkg lead-free part numbers to ordering info section.
Changed frequency of 225 MHz into 250 MHz
Added t
CYC
of 4.0 ns for 250 MHz
Changed
Θ
JA
and
Θ
JC
for TQFP Package
from 25 and 9
°
C/W to 29.41 and
6.13
°
C/W respectively
Changed
Θ
JA
and
Θ
JC
for BGA Package
from 25 and 6
°
C/W to 34.1 and
14.0
°
C/W respectively
Changed
Θ
JA
and
Θ
JC
for FBGA Package
from 27 and 6
°
C/W to 16.8 and
3.0
°
C/W respectively
Modified address expansion as per JEDEC Standard
Removed comment of Lead-free BG and BZ packages availability
*B
248929
See ECN
VBL
*C
323636
See ECN
PCI
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