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參數資料
| 型號： | ICY7C1362C-166BZI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 9-Mbit (256K x 36/512K x 18) Pipelined SRAM |
| 中文描述： | 512K X 18 CACHE SRAM, 3.5 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.40 HEIGHT, FBGA-165 |
| 文件頁數： | 15/31頁 |
| 文件大小： | 432K |
| 代理商： | ICY7C1362C-166BZI |
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PRELIMINARY
CY7C1360C
CY7C1362C
Document #: 38-05540 Rev. *C
Page 15 of 31
V
OL2
Output LOW Voltage
I
OL
= 100 μA
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
DDQ
= 3.3V
V
DDQ
= 2.5V
0.2
0.2
V
V
V
V
V
V
μA
V
IH
Input HIGH Voltage
2.0
1.7
–0.5
–0.3
–5
V
DD
+ 0.3
V
DD
+ 0.3
0.7
0.7
5
V
IL
Input LOW Voltage
I
X
Input Load Current
GND < V
IN
< V
DDQ
Identification Register Definitions
Instruction Field
CY7C1360C
(256KX36)
000
01011
000000
100110
00000110100
1
CY7C1362C
(512KX18)
000
01011
000000
010110
00000110100
1
Description
Revision Number (31:29)
Device Depth (28:24)
[13]
Device Width (23:18)
Cypress Device ID (17:12)
Cypress JEDEC ID Code (11:1)
ID Register Presence Indicator (0)
Describes the version number
Reserved for Internal Use
Defines memory type and architecture
Defines width and density
Allows unique identification of SRAM vendor
Indicates the presence of an ID register
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; VDD = 3.3V ±0.165V unless otherwise noted) (continued)
[12]
Parameter
Description
Conditions
Min.
Max.
Unit
Scan Register Sizes
Register Name
Bit Size (x36)
3
1
32
71
71
Bit Size (x18)
3
1
32
71
71
Instruction
Bypass
ID
Boundary Scan Order (119-ball BGA package)
Boundary Scan Order (165-ball fBGA package)
Identification Codes
Instruction
EXTEST
Code
000
Description
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state.
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
IDCODE
001
SAMPLE Z
010
RESERVED
SAMPLE/PRELOAD
011
100
RESERVED
RESERVED
BYPASS
101
110
111
Notes:
12.All voltages referenced to V
(GND).
13.Bit #24 is “1” in the Register Definitions for both 2.5v and 3.3v versions of this device.
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