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參數(shù)資料
| 型號： | ICY7C1362C-166BZI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 9-Mbit (256K x 36/512K x 18) Pipelined SRAM |
| 中文描述： | 512K X 18 CACHE SRAM, 3.5 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.40 HEIGHT, FBGA-165 |
| 文件頁數(shù)： | 10/31頁 |
| 文件大?。?/td> | 432K |
| 代理商： | ICY7C1362C-166BZI |
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PRELIMINARY
CY7C1360C
CY7C1362C
Document #: 38-05540 Rev. *C
Page 10 of 31
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
External
External
External
Next
Next
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
L
L
L
X
X
H
H
X
H
X
X
H
H
X
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
L
L
L
L
L
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
L
H
H
H
H
L
L
X
L
H
L
H
L
H
X
X
L
H
L
H
X
X
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
D
Q
Three-State
Q
Three-State
Q
Three-State
D
D
Q
Three-State
Q
Three-State
D
D
Partial Truth Table for Read/Write
[5, 9]
Function (CY7C1360C)
GW
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
BWE
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
BW
D
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
X
BW
C
X
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
X
BW
B
X
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
X
BW
A
X
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
X
Read
Read
Write Byte A – (DQ
A
and DQP
A
)
Write Byte B – (DQ
B
and DQP
B
)
Write Bytes B, A
Write Byte C – (DQ
C
and DQP
C
)
Write Bytes C, A
Write Bytes C, B
Write Bytes C, B, A
Write Byte D – (DQ
D
and DQP
D
)
Write Bytes D, A
Write Bytes D, B
Write Bytes D, B, A
Write Bytes D, C
Write Bytes D, C, A
Write Bytes D, C, B
Write All Bytes
Write All Bytes
Note:
9. Table only lists a partial listing of the byte write combinations. Any combination of BW
X
is valid. Appropriate write will be done based on which byte write is active.
Truth Table
(continued)
[3, 4, 5, 6, 7, 8]
Operation
Address
Used
CE
1
CE
2
CE
3
ZZ
ADSP ADSC ADV WRITE
OE CLK
DQ
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ICY7C1367B-166BGI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:9-Mb (256K x 36/512K x 18) Pipelined DCD Sync SRAM |
| ICY7C1373C-100BGI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture |
| ICY7C1373D-100BGI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture |
| ICY7C1373D-100BGXI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture |
| ICY7C1387C-167BGI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM |
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