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參數(shù)資料
| 型號： | ICY7C1362C-166BZI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 9-Mbit (256K x 36/512K x 18) Pipelined SRAM |
| 中文描述： | 512K X 18 CACHE SRAM, 3.5 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.40 HEIGHT, FBGA-165 |
| 文件頁數(shù)： | 21/31頁 |
| 文件大?。?/td> | 432K |
| 代理商： | ICY7C1362C-166BZI |
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PRELIMINARY
CY7C1360C
CY7C1362C
Document #: 38-05540 Rev. *C
Page 21 of 31
t
CLZ
t
CHZ
t
OEV
t
OELZ
t
OEHZ
Set-up Times
t
AS
t
ADS
t
ADVS
t
WES
t
DS
t
CES
Hold Times
t
AH
t
ADH
t
ADVH
t
WEH
t
DH
t
CEH
Shaded areas contain advance information.
Clock to Low-Z
[20, 21, 22]
Clock to High-Z
[20, 21, 22]
OE LOW to Output Valid
OE LOW to Output Low-Z
[20, 21, 22]
OE HIGH to Output High-Z
[20, 21, 22]
1.25
1.25
1.25
ns
1.25
2.8
2.8
1.25
3.0
3.0
1.25
3.5
3.5
ns
ns
ns
ns
0
0
0
2.8
3.0
3.5
Address Set-up before CLK Rise
ADSC, ADSP Set-up before CLK Rise
ADV Set-up before CLK Rise
GW, BWE, BW
X
Set-up before CLK Rise
Data Input Set-up before CLK Rise
Chip Enable Set-Up before CLK Rise
1.4
1.4
1.4
1.4
1.4
1.4
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
Address Hold after CLK Rise
ADSP, ADSC Hold after CLK Rise
ADV Hold after CLK Rise
GW, BWE, BW
X
Hold after CLK Rise
Data Input Hold after CLK Rise
Chip Enable Hold after CLK Rise
0.4
0.4
0.4
0.4
0.4
0.4
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
Notes:
19.This part has a voltage regulator internally; t
POWER
is the time that the power needs to be supplied above V
DD
(minimum) initially before a Read or Write operation
can be initiated.
20.t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
21.At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
22.This parameter is sampled and not 100% tested.
Switching Characteristics
Over the Operating Range (continued)
[17, 18]
Parameter
Description
250 MHz
Min.
200 MHz
Min.
166 MHz
Min.
Unit
Max
Max
Max
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| ICY7C1373D-100BGXI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture |
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