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參數(shù)資料
| 型號(hào)： | ICY7C1362C-166BZI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 9-Mbit (256K x 36/512K x 18) Pipelined SRAM |
| 中文描述： | 512K X 18 CACHE SRAM, 3.5 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.40 HEIGHT, FBGA-165 |
| 文件頁(yè)數(shù)： | 22/31頁(yè) |
| 文件大?。?/td> | 432K |
| 代理商： | ICY7C1362C-166BZI |
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PRELIMINARY
CY7C1360C
CY7C1362C
Document #: 38-05540 Rev. *C
Page 22 of 31
Switching Waveforms
Read Cycle Timing
[23]
Note:
23.On this diagram, when CE is LOW: CE
1
is LOW, CE
2
is HIGH and CE
3
is LOW. When CE is HIGH: CE
1
is HIGH or CE
2
is LOW or CE
3
is HIGH.
tCYC
tCL
CLK
ADSP
tADH
tADS
ADDRESS
tCH
OE
ADSC
CE
tAH
tAS
A1
tCEH
tCES
GW, BWE,
BWx
Data Out (Q)
High-Z
tCLZ
tDOH
tCO
tOEHZ
tCO
Single READ
BURST READ
tOEV
tOELZ
tCHZ
ADV
suspends
burst.
Burst wraps around
to its initial state
tADVH
tADVS
tWEH
tWES
tADH
tADS
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A1)
Q(A2)
Q(A2 + 1)
Q(A2 + 3)
A2
A3
Deselect
cycle
Burst continued with
new base address
DON’T CARE
UNDEFINED
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相關(guān)代理商/技術(shù)參數(shù) |
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| ICY7C1367B-166BGI | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:9-Mb (256K x 36/512K x 18) Pipelined DCD Sync SRAM |
| ICY7C1373C-100BGI | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture |
| ICY7C1373D-100BGI | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture |
| ICY7C1373D-100BGXI | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture |
| ICY7C1387C-167BGI | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM |
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