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參數(shù)資料
| 型號： | IBM13M8734HCC |
| 廠商： | IBM Microeletronics |
| 英文描述： | 8M x 72 1 Bank Registered/Buffered SDRAM Module(8M x 72 1組寄存/緩沖同步動態(tài)RAM模塊) |
| 中文描述： | 8米× 72 1銀行注冊/緩沖內(nèi)存模組（8米× 72 1組寄存/緩沖同步動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 18/21頁 |
| 文件大?。?/td> | 543K |
| 代理商： | IBM13M8734HCC |
IBM13M8734HCC
8M x 72 1 Bank Registered/Buffered SDRAM Module
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 18 of 21
19L7145.E93758B
2/99
Functional Description and Timing Diagrams
Refer to IBM 168 Pin SDRAM Registered DIMM Functional Description and Timing Diagrams (Document
01L5868.E24564) for registered-mode operation.
Refer to the IBM 64Mb Synchronous DRAM datasheet (Document 19L3264.E35855A) for the functional
description and timing diagrams for buffered-mode operation.
Refer to the IBM Application Notes Serial Presence Detect on Memory DIMMsand SDRAM Presence Detect
Definitions for the Serial Presence Detect functional description and timings.
t
f
SDA and SCL Fall Time
300
ns
t
SU:STO
Stop Condition Setup Time
4.7
μ
s
t
DH
Data Out Hold Time
300
ns
t
WR
Write Cycle Time
15
ms
1
Presence Detect Read and Write Cycle
Symbol
Parameter
Min.
Max.
Units
Notes
1. The write cycle time (t
WR
) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle.
During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and
the device does not respond to its slave address.
Discontinued (8/99 - last order; 12/99 - last ship)
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