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參數(shù)資料
| 型號： | IBM13M8734HCC |
| 廠商： | IBM Microeletronics |
| 英文描述： | 8M x 72 1 Bank Registered/Buffered SDRAM Module(8M x 72 1組寄存/緩沖同步動態(tài)RAM模塊) |
| 中文描述： | 8米× 72 1銀行注冊/緩沖內(nèi)存模組（8米× 72 1組寄存/緩沖同步動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 17/21頁 |
| 文件大?。?/td> | 543K |
| 代理商： | IBM13M8734HCC |
IBM13M8734HCC
8M x 72 1 Bank Registered/Buffered SDRAM Module
19L7145.E93758B
2/99
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 17 of 21
Read Cycle
Symbol
Parameter
-260
-360
-10
Units
Notes
Min.
Max.
Min.
Max.
Min.
Max.
t
OH
Data Out Hold Time
3.6
3.6
3.6
ns
t
LZ
Data Out to Low Impedance Time
1.9
1.9
1.9
ns
t
HZ
Data Out to High Impedance Time
4.9
9.9
4.9
9.9
4.9
11.9
ns
1
t
DQZ
DQM Data Out Disable Latency
Registered
3
3
3
CLK
Buffered
2
2
2
CLK
1. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.
Write Cycle
Symbol
Parameter
-260
-360
-10
Units
Min.
Max.
Min.
Max.
Min.
Max.
t
DS
Data In Setup Time
2.0
2.0
3.0
ns
t
DH
Data In Hold Time
2.0
2.0
2.0
ns
t
DPL2
Data Input to Precharge
20
20
0
ns
t
DPL3
Data Input to Precharge
10
10
0
ns
t
DQW
DQM Write Mask Latency
Registered
1
1
1
CLK
Buffered
0
0
0
CLK
Presence Detect Read and Write Cycle
Symbol
Parameter
Min.
Max.
Units
Notes
f
SCL
SCL Clock Frequency
100
kHz
T
I
Noise Suppression Time Constant at SCL, SDA Inputs
100
ns
t
AA
SCL Low to SDA Data Out Valid
0.3
3.5
μ
s
t
BUF
Time the Bus Must Be Free before a New Transmission Can Start
4.7
μ
s
t
HD:STA
Start Condition Hold Time
4.0
μ
s
t
LOW
Clock Low Period
4.7
μ
s
t
HIGH
Clock High Period
4.0
μ
s
t
SU:STA
Start Condition Setup Time (for a Repeated Start Condition)
4.7
μ
s
t
HD:DAT
Data In Hold Time
0
μ
s
t
SU:DAT
Data In Setup Time
250
ns
t
r
SDA and SCL Rise Time
1
μ
s
1. The write cycle time (t
WR
) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle.
During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and
the device does not respond to its slave address.
Discontinued (8/99 - last order; 12/99 - last ship)
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