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參數(shù)資料
| 型號(hào)： | IBM13M64734BCA |
| 廠商： | IBM Microeletronics |
| 英文描述： | 64M x 72 1 Bank Registered/Buffered SDRAM Module(64M x 72 1組寄存/緩沖同步動(dòng)態(tài)RAM模塊) |
| 中文描述： | 64米× 72 1銀行注冊(cè)/緩沖內(nèi)存模組（64米× 72 1組寄存/緩沖同步動(dòng)態(tài)內(nèi)存模塊） |
| 文件頁(yè)數(shù)： | 5/20頁(yè) |
| 文件大?。?/td> | 499K |
| 代理商： | IBM13M64734BCA |
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IBM13M64734BCA
Preliminary
64M x 72 1 Bank Registered/Buffered SDRAM Module
19L7159.E93855
2/00
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 5 of 20
Clock Wiring
10 Ohms
CK0
Clock Net Wiring (CK0):
IN
SDRAM
SDRAM
All PLL clock SDRAM loads are equal--
achieved in part through equal-length
wiring.
FDBK
IN
(PLL out to Feedback input)
10 Ohms
CK1, CK2, and CK3
Terminated Clock Nets (CK1, CK2, CK3):
PCK
OUT1
to
OUT6
OUT10
12pF
Phase
Lock
Loop
1. The PLL is programmed via a combination
of the feedback path and on-DIMM loading.
PLL feedback produces zero phase shift
from the delayed CK0 input.
2. Card wiring and capacitance loading varia-
tion:
±
100 ps.
3. Timing is based on a driver with a 1 Volt/ns
rise time.
Notes:
SDRAM
Register 1:1
Register 1:1
OUT7
PCK
One of six SDRAM outputs is shown.
12pF
12pF
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