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參數(shù)資料
| 型號(hào)： | IBM13M64734BCA |
| 廠商： | IBM Microeletronics |
| 英文描述： | 64M x 72 1 Bank Registered/Buffered SDRAM Module(64M x 72 1組寄存/緩沖同步動(dòng)態(tài)RAM模塊) |
| 中文描述： | 64米× 72 1銀行注冊(cè)/緩沖內(nèi)存模組（64米× 72 1組寄存/緩沖同步動(dòng)態(tài)內(nèi)存模塊） |
| 文件頁(yè)數(shù)： | 16/20頁(yè) |
| 文件大?。?/td> | 499K |
| 代理商： | IBM13M64734BCA |
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IBM13M64734BCA
64M x 72 1 Bank Registered/Buffered SDRAM Module
Preliminary
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 16 of 20
19L7159.E93855
2/00
Refresh Cycle
Symbol
Parameter
-260
-360
Units Notes
Min.
Max.
Min.
Max.
t
REF
Refresh Period
—
64
—
64
ms
1
1. 8192 cycles.
Read Cycle
Symbol
Parameter
-260
-360
Units
Notes
Min.
Max.
Min.
Max.
t
OH
Data Out Hold Time
3.6
—
3.6
—
ns
t
LZ
Data Out to Low Impedance Time
0.5
—
0.5
—
ns
t
HZ3
Data Out to High Impedance Time
3.5
6.7
3.5
6.7
ns
1
t
HZ2
Data Out to High Impedance Time
3.5
6.7
3.5
6.7
ns
1
t
DQZ
DQM Data Out Disable Latency
Registered
3
—
3
—
CLK
Buffered
2
—
2
—
CLK
1. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.
Write Cycle
Symbol
Parameter
-260
-360
Units
Min.
Max.
Min.
Max.
t
DS
Data In Setup Time
2.1
—
2.1
—
ns
t
DH
Data In Hold Time
1.6
—
1.6
—
ns
t
DPL
Data input to Precharge
Registered
10
—
10
—
ns
Buffered
20
20
t
DAL3
Data Input to Active, CL = 3
Registered
4
4
CLK
Buffered
5
5
t
DAL2
Data Input to Active, CL = 2
Registered
4
4
Buffered
5
5
t
DQW
DQM Write Mask Latency
Registered
1
—
1
—
CLK
Buffered
0
—
0
—
CLK
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