參數(shù)資料
型號(hào)： IBM13M32734CCB
廠商： IBM Microeletronics
英文描述： 32M x 72 1-Bank Registered / Buffered SDRAM Module(32M x 72 1組寄存/緩沖同步動(dòng)態(tài)RAM模塊)
中文描述： 32M × 72配置1，銀行注冊(cè)/緩沖內(nèi)存模組（32M × 72配置1組寄存/緩沖同步動(dòng)態(tài)內(nèi)存模塊）
文件頁(yè)數(shù)： 12/20頁(yè)
文件大?。?/td> 364K
代理商： IBM13M32734CCB
IBM13M32734CCB
32M x 72 1-Bank Registered / Buffered SDRAM Module
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 12 of 20
06K7740.H03381
04/00
Clock and Clock Enable Parameters
Symbol
Parameter
-75A max.
(Device CL
t
RCD
, t
RP
= 3, 3, 3)
Units
Notes
Min.
Max.
t
CK4
Clock Cycle Time, DIMM CAS Latency = 4
7.5
1000
ns
1
t
AC4
Clock Access Time, DIMM CAS Latency = 4
—
5.65
ns
1, 2
t
CKH
Clock High Pulse Width
2.5
—
ns
3
t
CKL
Clock Low Pulse Width
2.5
—
ns
3
t
CES
Clock Enable Setup Time
1.65
—
ns
1
t
CEH
Clock Enable Hold Time
0.35
—
ns
1
t
SB
Power Down Mode Entry Time
0
7.5
ns
t
T
Transition Time (Rise and Fall)
0.5
10
ns
1. DIMM CAS latency = device CL [clock cycles] + 1 for the Register mode.
2. Access time is measured at 1.4V. See AC output load circuit.
3. t
CKH
is the pulse width of CLK measured from the positive edge to the negative edge referenced to V
IH
(min). t
CKL
is the pulse
width of CLK measured from the negative edge to the positive edge referenced to V
IL
(max).
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