參數(shù)資料
型號(hào)： IBM13M32734BCC
廠商： IBM Microeletronics
英文描述： 32M x 72 2 Bank Registered SDRAM Module(32M x 72 2組寄存同步動(dòng)態(tài)RAM模塊)
中文描述： 32M × 72配置2銀行注冊(cè)內(nèi)存模塊（32M × 72配置2組寄存同步動(dòng)態(tài)內(nèi)存模塊）
文件頁(yè)數(shù)： 7/19頁(yè)
文件大小： 388K
代理商： IBM13M32734BCC
IBM13M32734BCC
Preliminary
32M x 72 2 Bank Registered SDRAM Module
88H5165.E24449
4/98
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 7 of 19
Serial Presence Detect (Part 1 of 2)
Byte #
Description
SPD Entry Value
Serial PD Data Entry
(Hexadecimal)
80
08
04
0C
0A
02
4800
01
A0
60
65
70
80
02
80
04
04
01
8F
04
06
01
01
IF
Notes
0
1
2
3
4
5
Number of Serial PD Bytes Written during Production
Total Number of Bytes in Serial PD device
Fundamental Memory Type
Number of Row Addresses on Assembly
Number of Column Addresses on Assembly
Number of DIMM Banks
Data Width of Assembly
Assembly Voltage Interface Levels
SDRAM Device Cycle Time (CL = 3)
128
256
SDRAM
12
10
2
x72
LVTTL
10.0ns
6.0ns
6.5ns
7.0ns
8.0ns
ECC
6 - 7
8
9
1, 2
10
SDRAM Device Access Time from Clock
at CL=3
-360
-365
-370
-10
11
12
13
14
15
16
17
18
19
20
21
Assembly Error Detection/Correction Scheme
Assembly Refresh Rate/Type
SDRAM Device Width
Error Checking SDRAM Device Width
SDRAM Device Attr: Min Clk Delay, Random Col Access
SDRAM Device Attributes: Burst Lengths Supported
SDRAM Device Attributes: Number of Device Banks
SDRAM Device Attributes: CAS Latency
SDRAM Device Attributes: CS Latency
SDRAM Device Attributes: WE Latency
SDRAM Module Attributes
SR/1X(15.625us)
x4
x4
1 Clock
1,2,4,8, Full Page
4
2, 3
0
0
Registered/Buffered with PLL
Write-1/Read Burst, Precharge
All, Auto-Precharge
15.0ns
22
SDRAM Device Attributes: General
0E
23
Minimum Clock Cycle at CLX-1 (CL = 2)
Maximum Data Access Time (t
AC
) from Clock at CLX-1 (CL = 2)
Minimum Clock Cycle Time at CLX-2 (CL = 1)
Maximum Data Access Time (t
AC
) from Clock at CLX-2 (CL = 1)
F0
1, 2
24
9.0ns
90
25
N/A
00
26
N/A
00
27
Minimum Row Precharge Time (t
RP
)
-360, -365, -370
-10
20.0ns
30.0ns
14
1E
28
Minimum Row Active to Row Active delay (t
RRD
)
20.0ns
14
29
Minimum RAS to CAS delay (t
RCD
)
-360, -365, -370
-10
-360, -365, -370
-10
20.0ns
30.0ns
50.0ns
60.0ns
128MB
14
1E
32
3C
20
20
30
Minimum RAS Pulse width (t
RAS
)
31
Module Bank Density
32
Address and Command Setup Time Before
Clock
-360, -365, -370
2.0ns
-10
Undefined
00
1. In a registered DIMM, data is delayed an additional clock cycle due to the on-DIMM pipeline register (i.e., Device CL [clock cycles]
+ 1 = DIMM CAS latency).
2. Minimum application clock cycle time for the -360, -365, -370 is 10ns (100MHz), and for -10 is 15ns (66MHz).
3. cc = Checksum Data byte, 00-FF (Hex)
4. “R” = Alphanumeric revision code, A-Z, 0-9
5. rr = ASCII coded revision code byte “R”
6. ww = Binary coded decimal week code, 01-52 (Decimal)
01-34 (Hex)
7. yy = Binary coded decimal year code, 00-99 (Decimal)
00-63 (Hex)
8. ss = Serial number data byte, 00-FF (Hex)
9. This table displays an example of the Assembly Part Numbers available.
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