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參數(shù)資料
| 型號(hào)： | IBM13M32734BCC |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32M x 72 2 Bank Registered SDRAM Module(32M x 72 2組寄存同步動(dòng)態(tài)RAM模塊) |
| 中文描述： | 32M × 72配置2銀行注冊(cè)內(nèi)存模塊（32M × 72配置2組寄存同步動(dòng)態(tài)內(nèi)存模塊） |
| 文件頁(yè)數(shù)： | 5/19頁(yè) |
| 文件大?。?/td> | 388K |
| 代理商： | IBM13M32734BCC |
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IBM13M32734BCC
Preliminary
32M x 72 2 Bank Registered SDRAM Module
88H5165.E24449
4/98
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 5 of 19
Clock Wiring
10 Ohm
CK0
Clock Net Wiring (CK0):
27pf
IN
SDRAM STACK
(2 DEVICES)
SDRAM STACK
(2 DEVICES)
One of 9 SDRAM outputs shown.
All PLL clock SDRAM loads equal.
Achieved in part through equal-length
wiring.
FDBK
IN
(PLL out to Feedback input)
10 0hms
CK1, CK2, and CK3
Terminated Clock Nets (CK1, CK2, and CK3):
PCK
(2 SDRAM stack modules,
4 device loads per output)
OUT1
TO
OUT9
24pf
OUT11
30pf
Phase
Lock
Loop
1. The PLL is programmed via a combination
of the feedback path and on-DIMM load-
ing. PLL feedback produces zero phase
shift from the delayed CK0 input.
2. Card wiring and capacitance loading varia-
tion:
±
100 ps
3. Timing is based on a driver with a 1 Volt/ns
rise time
Notes:
REG1 (1:1)
REG2 (1:1)
REG3 (1:1)
OUT10
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