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參數(shù)資料
| 型號(hào)： | IBM13M32734BCC |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32M x 72 2 Bank Registered SDRAM Module(32M x 72 2組寄存同步動(dòng)態(tài)RAM模塊) |
| 中文描述： | 32M × 72配置2銀行注冊(cè)內(nèi)存模塊（32M × 72配置2組寄存同步動(dòng)態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 15/19頁 |
| 文件大?。?/td> | 388K |
| 代理商： | IBM13M32734BCC |
IBM13M32734BCC
Preliminary
32M x 72 2 Bank Registered SDRAM Module
88H5165.E24449
4/98
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 15 of 19
Functional Description and Timing Diagrams
Refer to IBM 168-Pin SDRAM Registered DIMM Functional Description and Timing Diagrams (Document
01L5868.E24564, Revised 1/98 for SDRAM operation).
Refer to the IBM Application Notes Serial Presence Detect on Memory DIMMsand SDRAM Presence Detect
Definitions for the Serial Presence Detect functional description and timings.
Read Cycle
Symbol
Parameter
-360/-365/-370
Min.
3.6
1.9
4.9
3
-10
Units
Notes
Max.
Min.
3.6
1.9
4.9
3
Max.
t
OH
t
LZ
t
HZ
t
DQZ
Data Out Hold Time
Data Out to Low Impedance Time
Data Out to High Impedance Time
DQM Data Out Disable Latency
ns
ns
ns
9.9
11.9
1
CLK
1. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.
Write Cycle
Symbol
Parameter
-360/-365/-370
Min.
2.0
2.0
20
10
1
-10
Units
Max.
Min.
3.0
2.0
0
0
1
Max.
t
DS
t
DH
t
DDL2
t
DPL
t
DQW
Data In Set-up Time
Data In Hold Time
Data Input to Precharge
Data input to Precharge
DQM Write Mask Latency
ns
ns
ns
ns
CLK
Presence Detect Read and Write Cycle
Symbol
f
SCL
T
I
t
AA
t
BUF
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
r
t
f
t
SU:STO
t
DH
t
WR
Parameter
Min.
Max.
100
100
3.5
Units
KHz
ns
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
ns
μ
s
ns
μ
s
ns
ms
Notes
SCL Clock Frequency
Noise Suppression Time Constant at SCL, SDA Inputs
SCL Low to SDA Data Out Valid
Time the Bus Must Be Free before a New Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time (for a Repeated Start Condition)
Data in Hold Time
Data in Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
Write Cycle Time
0.3
4.7
4.0
4.7
4.0
4.7
0
250
1
300
4.7
300
15
1
1. The write cycle time (t
WR
) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle.
During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and
the device does not respond to its slave address.
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