參數(shù)資料
型號: IBM04364ARLAD-5N
元件分類: SRAM
英文描述: 128K X 36 STANDARD SRAM, 5.5 ns, PBGA119
封裝: BGA-119
文件頁數(shù): 7/22頁
文件大?。?/td> 517K
代理商: IBM04364ARLAD-5N
IBM04184ARLAD
IBM04364ARLAD
Preliminary
128K x 36 & 256K x 18 SRAM
75H4338
Revised 2/99
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 15 of 22
List of IEEE 1149.1 standard violations:
7.2.1.b, e
7.7.1.a-f
10.1.1.b, e
10.7.1.a-d
Scan Register Denition
Register Name
Bit Size x18
Bit Size x36
Instruction
3
Bypass
1
ID
32
Boundary Scan *
51
70
* The Boundary Scan chain consists of the following bits:
36 or 18 bits for Data Inputs Depending on x18 or x36 Conguration
17 bits for SA0 - SA16 for x36, 18 bits for SA0 - SA17 for x18
4 bits for SBWa - SBWd in x36, 2 bits for SBWa and SBWb in x18
8 bits for K, K, SS, G, SW, ZZ, M1 and M2
5 bits for Place Holders
* K and K clocks connect to a differential receiver that generates a single-ended clock signal. This signal and its inverted value are used
for Boundary Scan sampling.
ID Register Denition
Part
Field Bit Number and Description
Revision Number
(31:28)
Device Density and
Conguration (27:18)
Vendor Denition
(17:12)
Manufacture JEDEC
Code (11:1)
Start
Bit(0)
256K x 18
0001
011 100 1011
001111
000 101 001 00
1
128K x 36
0001
011 010 1100
001111
000 101 001 00
1
Instruction Set
Code
Instruction
Notes
000
SAMPLE-Z
001
IDCODE
010
SAMPLE-Z
011
PRIVATE
100
SAMPLE
101
PRIVATE
110
PRIVATE
111
BYPASS
1. Places DQs in High-Z in order to sample all input data regardless of other SRAM inputs.
2. TDI is sampled as an input to the rst ID register to allow for the serial shift of the external TDI data.
3. BYPASS register is initiated to VSS when BYPASS instruction is invoked. The BYPASS register also holds the last serially loaded
TDI when exiting the Shift DR state.
4. SAMPLE instruction does not place DQs in High-Z.
5. This instruction is reserved for the exclusive use of IBM. Invoking this instruction may cause improper SRAM functionality.
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