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參數(shù)資料
| 型號： | IBM04364ARLAD-5N |
| 元件分類： | SRAM |
| 英文描述： | 128K X 36 STANDARD SRAM, 5.5 ns, PBGA119 |
| 封裝： | BGA-119 |
| 文件頁數(shù)： | 3/22頁 |
| 文件大小： | 517K |
| 代理商： | IBM04364ARLAD-5N |
IBM04184ARLAD
IBM04364ARLAD
Preliminary
128K x 36 & 256K x 18 SRAM
75H4338
Revised 2/99
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 11 of 22
Timing Diagram (Read and Write Cycles)
K
SS
SW
G
DQ
SA
tKHKH
A3
D2
Q3
D4
tKLKH
tKHKL
tKHQV
tAVKH
tKHAX
tSVKH
tKHSX
tKHWX
tWVKH
tKHQZ
SBW
tDVKH
tKHDX
tKLQV
Q2
A1
A2
A4
Q1
NOTES:
1. D2 is the input data written in memory location A2.
2. Q2 is output data read from the write buffer, as a result of address A2 being a match
from the last write cycle address.
tKHWX
tWVKH
tKHWX
tWVKH
tDVKH
tKHDX
tKLQX4
tKHQV
tKHQZ
A2
tGHQZ
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