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參數(shù)資料
| 型號(hào)： | IBM04364ARLAD-5N |
| 元件分類： | SRAM |
| 英文描述： | 128K X 36 STANDARD SRAM, 5.5 ns, PBGA119 |
| 封裝： | BGA-119 |
| 文件頁數(shù)： | 22/22頁 |
| 文件大?。?/td> | 517K |
| 代理商： | IBM04364ARLAD-5N |
IBM04184ARLAD
IBM04364ARLAD
Preliminary
128K x 36 & 256K x 18 SRAM
75H4338
Revised 2/99
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 9 of 22
AC Characteristics (T
A=0 to +85°C, VDD, 3.3V ±5%, VDDQ = 2.5V -5%/+10%)
Parameter
Symbol
-5N
-6P
-6F
-6N
Units
Notes
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Cycle Time
tKHKH
6.0
—
6.0
—
6.0
—
6.0
—
ns
Clock High Pulse Width
tKHKL
1.5
—
1.5
—
1.5
—
1.5
—
ns
Clock Low Pulse Width
tKLKH
1.5
—
1.5
—
1.5
—
1.5
—
ns
Clock High to Output Valid
tKHQV
—
5.5
—
6.0
—
6.5
—
7.0
ns
Clock Low to Output Valid
tKLQV
—
2.5
—
2.5
—
2.5
—
3.0
ns
Address Setup Time
tAVKH
0.5
—
0.5
—
0.5
—
0.5
—
ns
Address Hold Time
tKHAX
1.0
—
1.0
—
1.0
—
1.0
—
ns
Sync Select Setup Time
tSVKH
0.5
—
0.5
—
0.5
—
0.5
—
ns
Sync Select Hold Time
tKHSX
1.0
—
1.0
—
1.0
—
1.0
—
ns
Write Enables Setup Time
tWVKH
0.5
—
0.5
—
0.5
—
0.5
—
ns
Write Enables Hold Time
tKHWX
1.0
—
1.0
—
1.0
—
1.0
—
ns
Data In Setup Time
tDVKH
0.5
—
0.5
—
0.5
—
0.5
—
ns
Data In Hold Time
tKHDX
1.0
—
1.0
—
1.0
—
1.0
—
ns
Clock Low to Data Out Hold
Time
tKLQX
0.5
—
0.5
—
0.5
—
0.5
—
ns
Clock Low to Output Active
tKLQX4
0.5
—
0.5
—
0.5
—
0.5
—
ns
Clock High to Output High-Z
tKHQZ
—
2.5
—
2.5
—
2.5
—
3.0
ns
Output Enable to High-Z
tGHQZ
—
2.5
—
2.5
—
3.0
ns
Output Enable to Low-Z
tGLQX
0.5
—
0.5
—
0.5
—
0.5
—
ns
Output Enable to Output
Valid
tGLQV
—
2.5
—
2.5
—
2.5
—
3.0
ns
Sleep Mode Recovery TIme
tZZR
5.5
—
6
—
6
—
6
—
ns
Sleep Mode Enable TIme
tZZE
—
5.5
—
6.0
—
6.0
—
6.0
ns
2. This specication is for No Data Retention. For data integrity at least 200ns of Recovery Time is recommended coupled with a
0.5ns Set-up time around K clock.
3. Veried by design and tested without guardband.
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