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參數(shù)資料
| 型號： | IBM04364ARLAD-5N |
| 元件分類： | SRAM |
| 英文描述： | 128K X 36 STANDARD SRAM, 5.5 ns, PBGA119 |
| 封裝： | BGA-119 |
| 文件頁數(shù)： | 17/22頁 |
| 文件大?。?/td> | 517K |
| 代理商： | IBM04364ARLAD-5N |
IBM04184ARLAD
IBM04364ARLAD
128K x 36 & 256K x 18 SRAM
Preliminary
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 4 of 22
75H4338
Revised 2/99
SRAM Features
Late Write
Late Write function allows for write data to be registered one cycle after addresses and controls. This feature
eliminates one bus-turnaround cycle necessary when going from a Read to a Write operation. Late Write is
accomplished by buffering write addresses and data so that the write operation occurs during the next write
cycle. In the case a read cycle occurs after a write cycle, the address and write data information are stored
temporarily in holding registers. During the first write cycle preceded by a read cycle, the SRAM array will be
updated with the address and data from the holding registers. Read cycle addresses are monitored to deter-
mine if read data is to be supplied from the SRAM array or the write buffer. The bypassing of the SRAM array
data occurs on a byte by byte basis. When one byte is written during a write cycle, read data from the last
written address will have new byte data from the write buffer and remaining bytes from the SRAM array.
Mode Control
Mode control pins: M1 and M2 are used to select four different JEDEC standard read protocols. This SRAM
supports Register-Latch (M1 = VDD, M2 = VSS) protocols. Mode control inputs must be set with power-up and
must not change during SRAM operation.
Power Down Mode
Power Down Mode, or “Sleep Mode” is accomplished by switching asynchronous signal ZZ high. When the
SRAM is in Sleep Mode, the outputs will go to a High-Z state and the SRAM will draw standby current. SRAM
data will be preserved and a recovery time (tZZR) is required before the SRAM resumes to normal operation.
When powering the SRAM down inputs must be dropped first and VDDQ must be dropped before or simulta-
neously with VDD.
Power-Up Requirements
In order to guarantee the optimum internally regulated supply voltage, the SRAM requires 4
s of power-up
time after VDD reaches its operating range. Power up requirements for the SRAM are that Vdd must be pow-
ered before or simultaneously with VDDQ, then inputs after VDDQ. VDDQ limitation is that VDDQ should not
exceed VDD supply by more than 0.4V during power up.
Sleep Mode Operation
Sleep mode is a low power mode initiated by bringing the asynchronous ZZ pin HIGH. During sleep mode, all
other inputs are ignored and outputs are brought to a High-Z state. Sleep mode current and output High Z are
guaranteed after the specified sleep mode enable time. During sleep mode, the array data contents are pre-
served. Sleep mode must not be initiated until after all pending operations have completed, as any pending
operation is not guaranteed to properly complete after sleep mode is initiated. Sense amp data is lost. Normal
operation can be resumed by bringing ZZ low, but only after specified sleep mode recovery time.
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