參數(shù)資料
型號: HYS64T16000HDL-2.5-A
廠商: INFINEON TECHNOLOGIES AG
元件分類: DRAM
英文描述: 16M X 64 DDR DRAM MODULE, 0.4 ns, DMA200
封裝: GREEN, SODIMM-200
文件頁數(shù): 22/46頁
文件大?。?/td> 833K
代理商: HYS64T16000HDL-2.5-A
Data Sheet
26
Rev. 1.1, 2005-06
02182004-HWZ1-64OM
HYS64T[16/32/64]0xxxHDL–[2.5/3.7/5]–A
Small Outline DDR2 SDRAM Modules
Electrical Characteristics
Self-Refresh Current
CKE
≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING,
Data bus inputs are FLOATING.
I
DD6 current values are guaranteed up to TCASE of 85 °C max.
I
DD6
All Bank Interleave Read Current
All banks are being interleaved at minimum
t
RC without violating tRRD using a burst length of 4. Control
and address bus inputs are STABLE during DESELECTS.
I
out = 0 mA.
I
DD7
1)
V
DDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V
2)
I
DD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled.
3) Definitions for
I
DD see Table 20
4)
I
DD1, IDD4R and IDD7 current measurements are defined with the outputs disabled (IOUT = 0 mA). To achieve this on module
level the output buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to
HIGH.
5) For two rank modules: for all active current measurements the other rank is in Precharge Power-Down Mode
I
DD2P
6) For details and notes see the relevant INFINEON component data sheet
Table 20
Definitions for
I
DD
Parameter
Description
LOW
V
IN VIL(ac).MAX, HIGH is defined as VIN VIH(ac).MIN
STABLE
inputs are stable at a HIGH or LOW level
FLOATING
inputs are
V
REF = VDDQ /2
SWITCHING
inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address
and control signals, and inputs changing between HIGH and LOW every other data transfer (once
per cycle) for DQ signals not including mask or strobes
Table 19
I
DD Measurement Conditions (cont’d)
1)2)3)4)5)6)
Parameter
Symbol
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