參數(shù)資料
型號(hào)： HYS64T16000HDL-2.5-A
廠商： INFINEON TECHNOLOGIES AG
元件分類： DRAM
英文描述： 16M X 64 DDR DRAM MODULE, 0.4 ns, DMA200
封裝： GREEN, SODIMM-200
文件頁數(shù)： 11/46頁
文件大?。?/td> 833K
代理商： HYS64T16000HDL-2.5-A
Data Sheet
16
Rev. 1.1, 2005-06
02182004-HWZ1-64OM
HYS64T[16/32/64]0xxxHDL–[2.5/3.7/5]–A
Small Outline DDR2 SDRAM Modules
Electrical Characteristics
3.3
AC Characteristics
3.3.1
Speed Grade Definitions
Table 11
Supply Voltage Levels and DC Operating Conditions
Parameter
Symbol
Values
Unit
Note
Min.
Nom.
Max.
Device Supply Voltage
V
DD
1.7
1.8
1.9
V
Output Supply Voltage
V
DDQ
1.7
1.8
1.9
V
1)
1)Under all conditions, VDDQ must be less than or equal to VDD
Input Reference Voltage
V
REF
0.49 x
V
DDQ
0.5 x
V
DDQ
0.51 x
V
DDQ
V
2)
2)Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC).VREF is also expected to track noise in VDDQ.
SPD Supply Voltage
V
DDSPD
1.7
—
3.6
V
DC Input Logic High
V
IH (DC)
V
REF +0.125
—
V
DDQ +0.3
V
DC Input Logic Low
V
IL (DC)
– 0.30
—
V
REF –0.125
V
In / Output Leakage Current
I
L
– 5
5
A
3)
3)Input voltage for any connector pin under test of 0 V
≤ V
IN ≤ VDDQ + 0.3 V; all other pins at 0 V. Current is per pin
Table 12
Speed Grade Definition Speed Bins DDR2-800E
Speed Grade
DDR2–800
Unit
Note
IFX Sort Name
–2.5
CAS-RCD-RP latencies
6–6–6
t
CK
Parameter
Symbol
Min.
Max.
—
Clock Frequency
@ CL = 3
t
CK
3.75
8
ns
1)2)3)4)
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are
further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) only.
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS,
RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode
3) Inputs are not recognized as valid until
V
REF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is
recognized as low.
4) The output timing reference voltage level is
V
TT.
@ CL = 4
t
CK
3.75
8
ns
1)2)3)4)
@ CL = 5
t
CK
38
ns
1)2)3)4)
@ CL = 6
t
CK
2.5
8
ns
1)2)3)4)
Row Active Time
t
RAS
45
70000
ns
1)2)3)4)5)
5)
t
RAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is
equal to 9 x
t
REFI.
Row Cycle Time
t
RC
60
—
ns
1)2)3)4)
RAS-CAS-Delay
t
RCD
15
—
ns
1)2)3)4)
Row Precharge Time
t
RP
15
—
ns
1)2)3)4)
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