參數(shù)資料
型號: HYS64T16000HDL-2.5-A
廠商: INFINEON TECHNOLOGIES AG
元件分類: DRAM
英文描述: 16M X 64 DDR DRAM MODULE, 0.4 ns, DMA200
封裝: GREEN, SODIMM-200
文件頁數(shù): 14/46頁
文件大?。?/td> 833K
代理商: HYS64T16000HDL-2.5-A
Data Sheet
18
Rev. 1.1, 2005-06
02182004-HWZ1-64OM
HYS64T[16/32/64]0xxxHDL–[2.5/3.7/5]–A
Small Outline DDR2 SDRAM Modules
Electrical Characteristics
3.3.2
AC Timing Parameters
Table 14
Timing Parameter by Speed Grade - DDR2-800
Parameter
Symbol
DDR2-800
Unit
Note
1)2)3)4)5)6)
7)
Min.
Max.
DQ output access time from CK / CK
t
AC
–400
+400
ps
CAS A to CAS B command period
t
CCD
2—
t
CK
CK, CK high-level width
t
CH
0.45
0.55
t
CK
CKE minimum high and low pulse width
t
CKE
3—
t
CK
CK, CK low-level width
t
CL
0.45
0.55
t
CK
Auto-Precharge write recovery + precharge time
t
DAL
WR +
t
RP
t
CK
Minimum time clocks remain ON after CKE
asynchronously drops LOW
t
DELAY
t
IS + tCK + tIH
––
ns
DQ and DM input hold time (differential data strobe)
t
DH(base)
––
ps
DQ and DM input pulse width (each input)
t
DIPW
0.35
t
CK
DQS output access time from CK / CK
t
DQSCK
–350
+350
ps
DQS input low (high) pulse width (write cycle)
t
DQSL,H
0.35
t
CK
DQS-DQ skew (for DQS & associated DQ signals)
t
DQSQ
——
ps
Write command to 1st DQS latching transition
t
DQSS
– 0.25
+ 0.25
t
CK
DQ and DM input setup time (differential data strobe)
t
DS(base)
ps
DQS falling edge hold time from CK (write cycle)
t
DSH
0.2
t
CK
DQS falling edge to CK setup time (write cycle)
t
DSS
0.2
t
CK
Clock half period
t
HP
MIN. (
t
CL, tCH)
Data-out high-impedance time from CK / CK
t
HZ
t
AC.MAX
ps
Address and control input hold time
t
IH(base)
ps
Address and control input pulse width
(each input)
t
IPW
0.6
t
CK
Address and control input setup time
t
IS(base)
ps
DQ low-impedance time from CK / CK
t
LZ(DQ)
2 x
t
AC.MIN
t
AC.MAX
ps
DQS low-impedance from CK / CK
t
LZ(DQS)
t
AC.MIN
t
AC.MAX
ps
Mode register set command cycle time
t
MRD
2—
t
CK
OCD drive mode output delay
t
OIT
012
ns
Data output hold time from DQS
t
QH
t
HP tQHS
Data hold skew factor
t
QHS
400
ps
Average periodic refresh Interval
t
REFI
—7.8
s
8)
—3.9
s
9)
Auto-Refresh to Active/Auto-Refresh command period
t
RFC
75
ns
Precharge-All (4 banks) command period
t
RP
t
RP +1tCK
—ns
Read preamble
t
RPRE
0.9
1.1
t
CK
Read postamble
t
RPST
0.40
0.60
t
CK
Active bank A to Active bank B command period
t
RRD
7.5
ns
10)
10
ns
11)
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