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參數(shù)資料
| 型號： | HYE25L256160AF-75 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | CAP TANT 10UF 6.3V 20% SMD |
| 中文描述： | 片256Mbit移動- RAM的 |
| 文件頁數(shù)： | 18/55頁 |
| 文件大?。?/td> | 1053K |
| 代理商： | HYE25L256160AF-75 |
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HYE25L256160AC
256-Mbit Mobile-RAM
Functional Description
Data Sheet
18
V1.1, 2003-04-16
Auto Refresh
Auto Refresh is used during normal operation of the 256-Mbit Mobile-RAM and is analogous to CAS Before RAS
(CBR) Refresh in previous DRAM types. This command is nonpersistent, so it must be issued each time a refresh
is required. All banks must be precharged before applying any refresh mode. An on-chip address counter
increments the word and the bank addresses. This makes the address bits “Don’t Care” during an Auto Refresh
command.
The chip enters the Auto Refresh mode, when RAS and CAS are held low and CKE and WE are held high at a
clock edge. The mode restores word line after the refresh and no external precharge command is necessary. A
minimum
t
RC
time is required between two automatic refreshes in a burst refresh mode. The same rule applies to
any access command after the automatic refresh operation.
In Auto-Refresh mode all banks are refreshed, independendly of the fact that the partial array self-refresh has been
set or not.
Self Refresh
The chip has an on-chip timer that is used when the Self Refresh mode is entered. The self-refresh command is
asserted with RAS, CAS, and CKE low and WE high at a clock edge. All external control signals including the clock
are disabled. Returning CKE to high enables the clock and initiates the refresh exit operation. After the exit
command, at least one
t
RC
delay is required prior to any access command. The use of self refresh mode introduces
the possibility that an iternally timed event can be missed when CKE is raised for exit from self refresh mode. Upon
exit from self refresh an extra auto refresh command is recommended.
Low Power SDRAMs have the possibility to program the refresh period of the on-chip timer with the use of an
appropriate extended MRS command, depending on the maximum operation case temperature in the application.
In partial array self refresh mode only the selected banks will be refreshed. Data written to the non activated banks
will get lost after a period defined by tref.
DQM Function
DQM has two functions for data I/O read and write operations. During reads, when it turns to “high” at a clock edge,
data outputs are disabled and become high impedance after two clock periods (DQM Data Disable Latency
t
DQZ
).
It also provides a data mask function for writes. When DQM is activated, the write operation at the next clock is
prohibited (DQM Write Mask Latency
t
DQW
= zero clocks).
Suspend Mode
During normal access, CKE is held high enabling the clock. When CKE is low, it freezes the internal clock and
extends data read and write operations. One clock delay is required for mode entry and exit (Clock Suspend
Latency t
CSL
).
Power Down
In order to reduce standby power consumption, a power down mode is available. All banks must be precharged
before the Mobile-RAM can enter the Power Down mode. Once the Power Down mode is initiated by holding CKE
low, all receiver circuits except for CLK and CKE are gated off. The Power Down mode does not perform any
refresh operations, therefore the device can’t remain in Power Down mode longer than the Refresh period (
t
REF
)
of the device. Exit from this mode is performed by taking CKE “high”. One clock delay is required for power down
mode entry and exit.
Deep Power Down Mode
The Deep Power Down Mode is an unique function on Mobile RAMs with very low standby currents.
All internal voltage generators inside the Mobile RAMs are stopped and all memory data is lost in this mode. To
enter the Deep Power Down mode all banks must be precharged.
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