參數(shù)資料
型號(hào)： HYE25L256160AC
廠商： INFINEON TECHNOLOGIES AG
英文描述： 256-Mbit Mobile-RAM
中文描述： 256兆移動(dòng)RAM
文件頁(yè)數(shù)： 22/55頁(yè)
文件大?。?/td> 1053K
代理商： HYE25L256160AC
HYE25L256160AC
256-Mbit Mobile-RAM
Electrical Characteristics
Data Sheet
22
V1.1, 2003-04-16
Figure 4
Measurement Conditions for
t
AC
and
t
OH
CAS to CAS command delay
Refresh Cycle
Refresh period
Self refresh exit time
Read Cycle
Data output hold time
Data output from high to low impedance
t
LZ
Data output from low to high impedance
t
HZ
DQM data output disable latency
Write Cycle
Write recovery time
DQM write data mask latency
t
CCD
1
–
1
–
t
CK
–
t
REF
t
SREX
–
1
64
–
–
1
64
–
ms
t
CK
–
–
t
OH
3
0
3
–
–
–
8
2
3
1
3
–
–
–
7
2
ns
ns
ns
t
CK
4)7)8)
–
–
–
t
DQZ
t
WR
t
DQW
14
0
–
–
14
0
–
–
ns
t
CK
9)
–
1)
–25
°
C
≤
T
CASE
≤
+85
°
C; recommended operating conditions unless otherwise noted
2) For proper power-up see the operation section of this data sheet.
3) Symbol index 2 and 3 refer to CL = 2 and CL = 3.
4) AC timing tests are referenced to the 0.9 V crossover point. The transition time is measured between
V
IH
and
V
IL
. All AC
measurements assume
t
T
= 1 ns with the AC output load circuit (details will be defined later). Specified
t
AC
and
t
OH
parameters are measured with a 30 pF only, without any resistive termination and with a input signal of 1
V
/
ns
edge rate
(see
Figure 4
).
5) If clock rising time is longer than 1 ns, a time (
t
T
/2 - 0.5) ns has to be added to this parameter.
6) If
t
T
is longer than 1 ns, a time (
t
T
- 1) ns has to be added to this parameter.
7) These parameter account for the number of clock cycle and depend on the operating frequency of the clock, as follows:
the number of clock cycle = specified value of timing period (counted in fractions as a whole number)
8) Access time from clock
t
AC
is 4.6 ns for –7.5 components with no termination and 0 pF load,
Data out hold time
t
OH
is 1.8 ns for –7.5 components with no termination and 0 pF load.
9) The write recovery time of
t
WR
= 14 ns allows the use of one clock cycle for the write recovery time when the memory
operation frequency is equal or less than 72MHz. For all memory operation frequencies higher than 72MHz two clock
cycles for
t
WR
are mandatory. INFINEON recommends to use two clock cylces for the write recovery time in all applications.
Table 10
Parameter
AC Timing Characteristics
1)2)
(cont’d)
Symbol
–8
max.
–7.5
max.
Unit Note/ Test Condition
min.
min.
30 pF
I/O
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