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參數(shù)資料
| 型號： | HYE25L256160AC |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 256-Mbit Mobile-RAM |
| 中文描述： | 256兆移動RAM |
| 文件頁數(shù)： | 17/55頁 |
| 文件大?。?/td> | 1053K |
| 代理商： | HYE25L256160AC |
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Data Sheet
17
V1.1, 2003-04-16
HYE25L256160AC
256-Mbit Mobile-RAM
Functional Description
The Write command is used to initiate a burst write access to an active (open) row. The value on the BA1 and BA0
inputs selects the bank, and the address provided on inputs A9-A0 for x16 selects the starting column location.
The value on input A10/AP determines whether or not Auto Precharge is used. If Auto Precharge is selected, the
row being accessed is precharged at the end of the Write burst; if Auto Precharge is not selected, the row remains
open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DQM
input logic level appearing coincident with the data. If a given DQM signal is registered low, the corresponding data
is written to memory; if the DQM signal is registered high, the corresponding data inputs are ignored, and a Write
is not executed to that byte/column location.
Precharge
The Precharge command is used to deactivate (close) the open row in a particular bank or the open row(s) in all
banks. The bank(s) will be available for a subsequent row access a specified time (
t
RP
) after the Precharge
command is issued. When RAS and WE are low and CAS is high at a clock edge, it triggers the precharge
operation. Input A10 determines whether one or all banks are to be precharged, and in the case where only one
bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don’t Care” (see
Table 6
). Once a bank has been precharged, it is in the idle state and must be activated prior to any Read or Write
commands being issued to that bank. A precharge command is treated as a NOP if there is no open row in that
bank, or if the previously open row is already in the process of precharging.
The precharge command can be imposed one clock before the last data out for CAS latency = 2 and two clocks
before the last data out for CAS latency = 3. Writes require a time delay
t
WR
from the last data out to apply the
precharge command.
Auto Precharge
Auto Precharge is a feature which performs the same individual-bank precharge functions described above, but
without requiring an explicit command. This is accomplished by using A10/AP to enable Auto Precharge in
conjunction with a specific Read or Write command. A precharge of the bank/row that is addressed with the Read
or Write command is automatically performed upon completion of the Read or Write burst. Auto Precharge is
nonpersistent in that it is either enabled or disabled for each individual Read or Write command. Auto Precharge
ensures that the precharge is initiated at the earliest valid stage within a burst. The user must not issue another
command to the same bank until the precharge (
t
RP
) is completed. This is determined as if an explicit Precharge
command was issued at the earliest possible time. The 256-Mbit Mobile-RAM automatically enters the precharge
operation after
t
WR
(Write recovery time) following the last data in.
Burst Terminate
Once a burst read or write operation has been initiated, there are several methods used to terminate the burst
operation prematurely. These methods include using another Read or Write Command to interrupt an existing
burst operation, using a Precharge Command to interrupt a burst cycle and close the active bank, or using the
Burst Stop Command to terminate the existing burst operation but leave the bank open for future Read or Write
Commands to the same page of the active bank. When interrupting a burst with another Read or Write Command
care must be taken to avoid DQ contention. The Burst Stop Command, however, has the fewest restrictions
making it the easiest method to use when terminating a burst operation before it has been completed. If a Burst
Stop command is issued during a burst write operation, then any residual data from the burst write cycle will be
ignored. Data that is presented on the DQ pins before the Burst Stop Command is registered will be written to the
memory.
Table 6
A10
0
0
0
0
1
Bank Selection by Address Bits with Precharge
BA0
BA1
0
0
0
1
1
0
1
1
x
x
Bank 0
Bank 1
Bank 2
Bank 3
all Banks
相關(guān)PDF資料 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYE25L256160AC-7.5 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:BJAWBMSpecialty DRAMs Mobile-RAM |
| HYE25L256160AC-75 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256-Mbit Mobile-RAM |
| HYE25L256160AC-8 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256-Mbit Mobile-RAM |
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