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| 型號： | HYE18P32160AC-15 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | M39012 MIL RF CONNECTOR |
| 中文描述： | 32M的同步突發(fā)的CellularRAM |
| 文件頁數(shù)： | 39/53頁 |
| 文件大小： | 1426K |
| 代理商： | HYE18P32160AC-15 |
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–
0
–
–
2
Data Sheet
39
V2.0, 2003-12-16
HYE18P32160AC(-/L)9.6/12.5/15
32M Synchronous Burst CellularRAM
Functional Description
Table 15
Parameter
Timing Parameters - Synchronous Read Burst
Symbol
9.6
12.5
15
Unit
Notes
Min.
–
–
9.6
15
3
3
–
3
1.5
5
4
–
3.5
–
5
3
0
Max.
104
66
–
–
–
–
1.8
–
–
–
–
35
20
10
–
–
6
20
7
7
7
7
–
Min.
–
–
12.5
20
3.5
3.5
–
3.5
2
5
4
–
4
–
6
3
0
–
–
0
–
–
2
Max.
80
50
–
–
–
–
2
–
–
–
–
46.5
20
10
–
–
8
20
9
8
9
9
–
Min.
–
–
15
25
4
4
–
4
2
7
6
–
4
–
8
3
0
–
–
0
–
–
3
Max.
66
40
–
–
–
–
2
–
–
–
–
54
20
10
–
–
8
25
11
8
11
11
–
Clock period frequency
Lat = 3
f
CLK3
Lat = 2
f
CLK2
Lat = 3
t
CLK3
Lat = 2
t
CLK2
MHz –
MHz –
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μ
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock period
–
–
–
–
–
–
–
1)
Clock high time
Clock low time
Clock rise/fall time
Input setup time to CLK (except CS)
Input hold time from CLK
ADV pulse width high
ADV pulse width low
Burst read 1
st
access delay from CLK
CS low setup to CLK
Chip select pulse width low time
CS pulse width high
OE or LB/UB low to output low-Z
CS, OE, or LB/UB high to output high-Z
t
OD
OE low to output delay
CS low to WAIT valid
CS high to WAIT high-Z
CLK to WAIT valid
CLK to output delay
Output hold from CLK
t
CKH
t
CKL
t
T
t
SP
t
HD
t
VPH
t
VP
t
ABA
t
CSS
t
CSL
t
CBPH
t
OL
–
2)
3)
–
–
–
–
–
–
–
–
–
–
t
AOE
t
CWT
t
WZ
t
WK
t
ACLK
t
KOH
1) ADV low for new burst command can not be issued while the previous burst is in burst_init cycle (within latency).
2) In case of refresh collision to the first access, more WAIT cycles will be added.
3) For proper synchronous burst operation,
t
CSSmax
should be met. Otherwise, it is strongly recommended to use CellularRAM
in asynchronous mode of operation, instead.
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