參數(shù)資料
型號(hào): HYE18P32160AC-15
廠商: INFINEON TECHNOLOGIES AG
英文描述: M39012 MIL RF CONNECTOR
中文描述: 32M的同步突發(fā)的CellularRAM
文件頁(yè)數(shù): 34/53頁(yè)
文件大?。?/td> 1426K
代理商: HYE18P32160AC-15
HYE18P32160AC(-/L)9.6/12.5/15
32M Synchronous Burst CellularRAM
Functional Description
Data Sheet
34
V2.0, 2003-12-16
2.6.3
Writing to the device in asynchronous SRAM mode is accomplished by asserting the Chip Select (CS) and Write
Enable (WE) signals to low. ADV can be used to latch the address (refer to
“Asynchronous Write with Address
Latch (ADV) Control” on Page 40
for details) or simply held low for entire write operation. If the Upper Byte (UB)
control line is set active low then the upper word (DQ15 to DQ8) of the data bus is written to the specified memory
location. If the Lower Byte (LB) control line is set active low then the lower word (DQ7 to DQ0) of the data bus is
written to the specified memory location. Write operation takes place when either one or both UB and LB is
asserted low. The data is latched by the rising edge of either CS, WE, or UB/LB whichever signal comes first.
Asynchronous Write
Figure 16
Asynchronous Write - WE Controlled (OE =
V
IH
or
V
IL
, CRE =
V
IL
)
Figure 17
Asynchronous Write - CS Controlled (OE =
V
IH
or
V
IL
, CRE =
V
IL
)
Don't Care
A20-A0
ADDRESS
CS
WE
UB, LB
DQx IN
t
CW
t
WR
t
WC
t
WP
t
AW
t
BW
Data Valid
DQx OUT
t
DW
t
DH
t
AS
t
WHZ
t
OW
ADV
t
VPH
t
VS
t
WPH
Don't Care
A20-A0
ADDRESS
CS
WE
UB, LB
DQx OUT
t
CW
t
WC
t
AS
t
WP
t
DW
t
DH
t
BW
Data In Valid
DQx IN
High-Z
t
LZ,
t
BLZ
t
WHZ
ADV
t
CPH
t
WR
t
AW
t
VPH
t
VS
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