參數(shù)資料
型號(hào)： HYE18P32160AC-15
廠商： INFINEON TECHNOLOGIES AG
英文描述： M39012 MIL RF CONNECTOR
中文描述： 32M的同步突發(fā)的CellularRAM
文件頁(yè)數(shù)： 21/53頁(yè)
文件大小： 1426K
代理商： HYE18P32160AC-15
Data Sheet
21
V2.0, 2003-12-16
HYE18P32160AC(-/L)9.6/12.5/15
32M Synchronous Burst CellularRAM
Functional Description
2.3
Refresh Control Register
The Refresh Control Register (RCR) allows to save stand-by power additionally by making use of the
Temperature-Compensated Self Refresh (TCSR), Partial-Array Self Refresh (PASR) and Deep Power Down
(DPD) features. The Refresh Control Register is programmed via the Control Register Set command (with
CRE = 1 and A19 = 0) and retains the stored information until it is reprogrammed or the device loses power.
Please note that the RCR contents can only be set or changed when the CellularRAM is in idle state.
RCR
Refresh Control Register
(CRE, A19 = 10
B
)
A20
A19
A18
A17
A16
A15
A14 A13 A12 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
RS
0
PM
TCSR
DPD
0
PASR
Field
RS
Bits
19
Type
1)
Description
w
Register Select
0
w
Page Mode Enable/Disable
In asynchronous operation mode the user has the option to toggle A0 - A3 in a random
way at higher rate (20 ns vs. 70 ns) to lower access times of subsequent reads with
16-word boundary. In synchronous mode this option has no effect. The max. page
length is 16 words.
Please note that as soon as page mode is enabled the CS low time restriction applies.
This means that the CS signal must not be kept low longer than
t
CSL
= 10
μ
s. Please
refer to
Figure 15
.
0
page mode disabled (default)
1
page mode enabled
w
Temperature Compensated Self Refresh
The 2-bit wide TCSR field features four different temperature ranges to adjust the
refresh period to the actual case temperature. Since DRAM technology requires higher
refresh rates at higher temperature this is a second method to lower power
consumption in case of low or medium temperatures.
11
+85 °C (default)
00
+70 °C
01
+45 °C
10
+15 °C
w
Deep Power Down Enable/Disable
The DPD control bit puts the CellularRAM device in an extreme low power mode
cutting current consumption to less than 25
μ
A. Stored memory data is not retained in
this mode. Though the settings of both control registers RCR and BCR are also stored
during DPD.
0
DPD enabled
1
DPD disabled (default)
set to 0 to select this RCR (= 1 to select BCR).
PM
7
TCSR
[6:5]
DPD
4
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