參數(shù)資料
型號(hào)： HYB18L128160BC-7.5
廠商： INFINEON TECHNOLOGIES AG
英文描述： BJAWBMSpecialty DRAMs Mobile-RAM
中文描述： BJAWBMSpecialty DRAM的移動(dòng)RAM
文件頁數(shù)： 27/53頁
文件大小： 1328K
代理商： HYB18L128160BC-7.5
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional Description
Data Sheet
27
V1.4, 2004-04-30
2.4.5.3
DQM may be used to suppress read data and place the output buffers into High-Z state. The generic timing
parameters as listed in
Table 10
also apply to this DQM operation. The read burst in progress is not affected and
will continue as programmed.
READ - DQM Operation
Figure 20
READ Burst - DQM Operation
2.4.5.4
A READ burst may be followed by or truncated with a WRITE command. The WRITE command can be performed
to the same or a different (active) bank. Care must be taken to avoid bus contention on the DQs; therefore it is
recommended that the DQs are held in High-Z state for a minimum of 1 clock cycle. This can be achieved by either
delaying the WRITE command, or suppressing the data-out from the READ by pulling DQM HIGH two clock cycles
prior to the WRITE command, as shown in
Figure 21
. With the registration of the WRITE command, DQM acts as
a write mask: when asserted HIGH, input data will be masked and no write will be performed.
READ to WRITE
Figure 21
READ to WRITE Timing
Ba A, Col n = bank A, column n
DO n = Data Out from column n
CL = 2 in the case shown.
DQM read latency t
DQZ
is 2 clock cycles
= Don't Care
CLK
Command
NOP
READ
NOP
NOP
NOP
NOP
NOP
NOP
DQM
t
DQZ
Address
Ba A,
Col n
DQ
DO n+2
DO n
DO n+3
Ba A, Col n (b) = bank A, column n (b)
DO n = Data Out from column n; DI b = Data In to column b;
DQM is asserted HIGH to set DQs to High-Z state for 1 clock cycle prior to the WRITE command.
= Don't Care
CLK
CL=2
CL=3
Command
NOP
READ
NOP
NOP
NOP
NOP
NOP
WRITE
Address
Ba A,
Col b
Ba A,
Col n
DQM
DQ
DO n
DI b
DI b+1
DO n+1
High-Z
DI b+2
DQ
DI b
DI b+1
DO n
High-Z
DI b+2
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