參數(shù)資料
型號(hào)： HYB18L128160BC-7.5
廠商： INFINEON TECHNOLOGIES AG
英文描述： BJAWBMSpecialty DRAMs Mobile-RAM
中文描述： BJAWBMSpecialty DRAM的移動(dòng)RAM
文件頁數(shù)： 26/53頁
文件大?。?/td> 1328K
代理商： HYB18L128160BC-7.5
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional Description
Data Sheet
26
V1.4, 2004-04-30
2.4.5.1
Data from any READ burst may be truncated using the BURST TERMINATE command (see
Page 33
), provided
that Auto Precharge was not activated. The BURST TERMINATE latency is equal to the CAS latency, i.e. the
BURST TERMINATE command must be issued x clock cycles before the clock edge at which the last desired data
element is valid, where x equals the CAS latency for READ bursts minus 1. This is shown in
Figure 18
. The
BURST TERMINATE command may be used to terminate a full-page READ which does not self-terminate.
READ Burst Termination
Figure 18
Terminating a READ Burst
2.4.5.2
Clock suspend mode allows to extend any read burst in progress by a variable number of clock cycles. As long as
CKE is registered LOW, the following internal clock pulse(s) will be ignored and data on DQ will remain driven, as
shown in
Figure 19
.
Clock Suspend Mode for READ Cycles
Figure 19
Clock Suspend Mode for READ Bursts
Ba A, Col n = Bank A, Column n
DO n = Data Out from column n
Burst Length = 4 in the case shown.
2 subsequent elements of Data Out are provided in the programmed order following DO n.
The burst is terminated after the 3rd data element.
= Don't Care
CLK
CL=2
CL=3
Command
NOP
READ
NOP
NOP
NOP
NOP
NOP
BST
NOP
Address
Ba A,
Col n
DQ
DO n+1
DO n
DO n+2
DQ
DO n+1
DO n
DO n+2
Ba A, Col n etc. = Bank A, Column n etc.
DO n etc. = Data Out from column n etc.
CL = 2 in the case shown
Clock suspend latency t
CSL
is 1 clock cycle
= Don't Care
CLK
t
CSL
t
CSL
t
CSL
CKE
internal
clock
Command
READ
NOP
NOP
NOP
NOP
NOP
Ba A,
Col n
Address
DQ
DO n+2
DO n
DO n+1
DO n+1
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