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參數(shù)資料
| 型號： | HV7161SPA2 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | CMOS Image Sensor with Image Signal Processing |
| 中文描述： | 的CMOS圖像傳感器和圖像信號處理 |
| 文件頁數(shù)： | 7/72頁 |
| 文件大小： | 2023K |
| 代理商： | HV7161SPA2 |
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Confidential
HV7161SPA2
CMOS Image Sensor
With Image Signal Processing
This document has a general product description and is subject to change without notice.
MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described
and no patent licenses are implied.
- 7 -
2005 MagnaChip Semiconductor Ltd.
sleep mode register bit SCTRB[4] is low.
ENB low : sleep mode, ENB high : normal mode
Digital ground for I/O driver
1.8V digital power for I/O driver
AVDDPH 2.5V to 2.8V analog power for pixel block
AGNDC
Analog ground for analog block
AVDDC
1.8V analog power for analog block
Video frame synchronization signal. VSYNC is active at
start of image data frame.
Video horizontal line synchronization signal. Image data is
valid, when HSYNC is high.
VCLK
Video output clock
MCLK
Master input clock
DVDDIH
2.5V to 2.8V digital power for I/O driver
DGNDI
Digital ground for I/O driver
Pins 19-20, 33-35, 42-46 are not connected.
Pin function:
B - CMOS Schmitt trigger, non-inverted, tri-state bidirectional buffer, 4mA drive
I - CMOS Schmitt trigger level non-inverting input
O - Tri-state non-inverting output, 4mA drive (VCLK - 8mA drive)
PH - 2.5V to 2.8V I/O or pixel power, P - 1.8V digital or analog power
G - Universal ground
28
29
30
31
32
G
P
PH
G
P
DGNDI
DVDDI
36
O
VSYNC
37
O
HSYNC
38
39
40
41
O
I
PH
G
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