- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371906 > HV7161SPA2 (Electronic Theatre Controls, Inc.) CMOS Image Sensor with Image Signal Processing PDF資料下載
參數(shù)資料
| 型號(hào)： | HV7161SPA2 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | CMOS Image Sensor with Image Signal Processing |
| 中文描述： | 的CMOS圖像傳感器和圖像信號(hào)處理 |
| 文件頁數(shù)： | 56/72頁 |
| 文件大?。?/td> | 2023K |
| 代理商： | HV7161SPA2 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁當(dāng)前第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁
Confidential
HV7161SPA2
CMOS Image Sensor
With Image Signal Processing
This document has a general product description and is subject to change without notice.
MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described
and no patent licenses are implied.
- 56 -
2005 MagnaChip Semiconductor Ltd.
7
6
5
4
3
2
1
0
Reserved
PLL Feedback Divisor High
0
0
0
0
0
0
0
0
PLL Feedback Divisor Low [PFDDIVL : a5h : 02h]
7
6
5
4
3
2
1
0
PLL Feedback Divisor Low
0
0
0
0
0
0
1
0
The operation frequency of PLL is related to the proportion of Reference(PREFDIV) to
Feedback(PFDDIV) Divisor. F(ck) is actually determined by the following equation.
(
)
(
)
(
eference
R
)
(
)
Divisor
Divisor
Feedback
ref
F
ck
F
=
F(ck) : frequency of output
F(ref) : frequency of PLL input
Feedback Divisor : PFDDIV[13:0] + 2
Reference Divisor : PREFDIV[7:0] + 1
Data Output Timing and Interface
Y [7 :0 ]
V C L K
H S Y N C
X
Y 0
Y 1
Y 2
4 n s ~ 5 n s
1 4 n s ~ 1 5 ns
M C L K
As specified is the above data output timing diagram, the timing margin between video clock
pin(VCLK) and data pins(Y[7:0]) is about 4n~5ns. This margin may be sufficient or not according to
how much video clock and data pins are delayed internally in the backend chip, respectively. To
safely latch the data output in the backend chip, it is recommended that data be latched at
negative edge of VCLK.
The above timing margin diagram represents 16bit output interface, but is also valid for 8bit output
interface..
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HVC145 | Silicon Epitaxial Planar Pin Diode for Antenna Switching |
| HVC190 | Silicon Epitaxial Planar PIN Diode for High Frequency Attenuator |
| HVC380B | Variable Capacitance Diode for VCO |
| HVC381B | Variable Capacitance Diode for VCO |
| HVD144A | Silicon Epitaxial Trench Pin Diode for Antenna Switching |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HV71SM-142 | 制造商:APITECH 制造商全稱:APITECH 功能描述:Voltage Controlled Oscillator |
| HV71SM-32 | 制造商:SPECTRUM 制造商全稱:Spectrum Microwave, Inc. 功能描述:Voltage Controlled Oscillator |
| HV71T-14 | 制造商:SPECTRUM 制造商全稱:Spectrum Microwave, Inc. 功能描述:Voltage Controlled Oscillator |
| HV71T-3 | 制造商:SPECTRUM 制造商全稱:Spectrum Microwave, Inc. 功能描述:Voltage Controlled Oscillator |
| HV7224 | 制造商:SUPERTEX 制造商全稱:SUPERTEX 功能描述:40-Channel Symmetric Row Driver |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。