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參數(shù)資料
| 型號： | HV7161SPA2 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | CMOS Image Sensor with Image Signal Processing |
| 中文描述： | 的CMOS圖像傳感器和圖像信號處理 |
| 文件頁數(shù)： | 32/72頁 |
| 文件大小： | 2023K |
| 代理商： | HV7161SPA2 |
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Confidential
HV7161SPA2
CMOS Image Sensor
With Image Signal Processing
This document has a general product description and is subject to change without notice.
MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described
and no patent licenses are implied.
- 32 -
2005 MagnaChip Semiconductor Ltd.
7
6
5
4
3
2
1
0
Reserved
Bayer 11bit
Output
0
U First
Y First
16bit Bus
RGB 5:6:5
4:4:4
Format
0
24bit RGB
0
1
1
0
0
0
Bayer 11bit Output
If this bit is high, then 11bit Bayer raw values are continuously outputted
through output ports, Y0[7:0] = Bayer[10:3], Y1[2:0] = Bayer[2:0], else 8bit
Bayer raw only, Y[7:0] = Bayer[10:3]. And when this bit is high and 16bit bus
mode is enabled, Y[7:0] is outputted Bayer[10:3] and C[2:0] is outputted
Bayer[2:0]. For more information, refer page 62, Bayer data format.
Cb(B) pixel in front of Cr(R) pixel in 16bit or 8bit video data output modes.
Y pixel in front of Cb and Cr pixels in 8bit video output mode. This option is
meaningful only with YCbCr 4:2:2 8bit output mode.
If this bit is high, output format is 16bit mode(YCbCr 4:2:2, YCbCr 4:4:4, or
RGB 4:4:4), otherwise output format is 8bit mode(YCbCr 4:2:2, RGB 5:6:5,
Bayer).
Data format of RGB 5:6:5 mode is composed with {R[7:3]/G[7:5]} ,
{G[4:2]/B[7:3]} or {B[7:3]/G[7:5]}, {G[4:2]/R[7:3]}. OUTFMT[5](Cb/B First)
register affects above data form.
YCbCr 4:4:4 or RGB 4:4:4 24bit data for a pixel is produced with 16bit
output mode. (16bit Bus = '1')
R,G,B 4:4:4 24bit data for a pixel is produced with 16bit output mode.(16bit
Bus = '1' and 4:4:4 Format = '1')
Default mode of Output Format is YCbCr 4:2:2 8bit bus mode.
Output Signal Inversion [OUTINV : 32h : 00h]
7
6
5
4
U First
Y First
16Bit Bus
RGB 5:6:5
4:4:4 Format
24Bit RGB
3
2
1
0
Reserved
Clocked
HSYNC
0
VSYNC
inversion
0
HSYNC
inversion
0
VCLK
inversion
0
0
0
0
0
Clocked HSYNC
In HSYNC, VCLK is embedded, that is, HSYNC is toggling at VCLK rate
during normal HSYNC time
VSYNC output polarity is inverted
HSYNC output polarity is inverted
VCLK output polarity is inverted
VSYNC inversion
HSYNC inversion
VCLK inversion
Dark Noise Cancellation [DNCMODE : 33h : 21h]
7
6
DNC Always Performing Zone
0
0
5
4
3
DNC Threshold
0
2
1
0
DNC Mode
1
0
0
0
1
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