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| 型號： | HV7161SPA2 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | CMOS Image Sensor with Image Signal Processing |
| 中文描述： | 的CMOS圖像傳感器和圖像信號處理 |
| 文件頁數(shù)： | 16/72頁 |
| 文件大?。?/td> | 2023K |
| 代理商： | HV7161SPA2 |
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Confidential
HV7161SPA2
CMOS Image Sensor
With Image Signal Processing
saturation level is user-programmable.
Edge enhancement
Edge enhancement is performed for increasing sharpness of image. Edge weight factor is user-
programmable.
Special image functions
Special image functions support the negative, mono, gray, level, and sepia image.
Frame Timing
For clear description of frame timing, clocks’ acronym and relation are reminded in here again.
< Clock Acronym Definition >
MCP : Master Clock Period
SCP : Sensor Clock Period
VCP : Video Clock Period
< Clock Frequency Relation >
MCP : MCP
This document has a general product description and is subject to change without notice.
MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described
and no patent licenses are implied.
- 16 -
2005 MagnaChip Semiconductor Ltd.
DCP : Divided Clock Period
ICP : Image Processing Clock Period
LCP : Line Clock Period
DCP : MCP * Clock Division
SCP for color interpolation,
SCP * 2 for 1/4 subsampling mode
SCP * 4 for 1/16 subsampling mode
SCP : DCP * 2
ICP
VCP : ICP for 16bit output, ICP / 2 for 8bit
output
HBLANK Period : HBLANK Time register value * SCP
HSYNC Period : HSYNC Active Time
< Frame Time Calculation >
Core Frame Time is (IDLE SLOT + Video Height * LCP), and Real Frame Time is resolved as
follows.
When Integration Time > Core Frame Time, Real Frame Time is (Integration Time + VBLANK *
LCP),
otherwise is (Core Frame Time + VBLANK * LCP).
If Integration Time < Core Frame Time, Real Frame Time is
{(1280 + 214) * ( 960 + 10) + SCTRC[0] * 4928} * SCP = 1454108 * 47.62ns = 0.069245sec,
else Real Frame Time is
{Integration Time + 8 * (208 + 1280) } * SCP.
1. 1/4 Sub-sampling Timing
In 1/4 subsampling mode, valid video data is produced every other line, i.e. for 960 lines, active
video lines are 432 lines. HSYNC active time is equal to HSYNC active time of color interpolation
LCP : HBLANK Period + HSYNC Period
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