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| 型號： | HV7161SPA2 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | CMOS Image Sensor with Image Signal Processing |
| 中文描述： | 的CMOS圖像傳感器和圖像信號處理 |
| 文件頁數(shù)： | 25/72頁 |
| 文件大?。?/td> | 2023K |
| 代理商： | HV7161SPA2 |
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Confidential
HV7161SPA2
CMOS Image Sensor
With Image Signal Processing
This document has a general product description and is subject to change without notice.
MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described
and no patent licenses are implied.
- 25 -
2005 MagnaChip Semiconductor Ltd.
high.
When strobe signal is enabled by this bit, STROBE pin will indicates when
strobe light should be splashed in the dark environment to get adequate
lighted image.
Divides input master clock(IMC) for internal use. Internal divided clock
frequency(DCF) is defined as master clock frequency(MCF) divided by
specified clock divisor. Internal divided clock frequency(DCF) is as follows.
000 : MCF, 001 : MCF/2, 010 : MCF/4, 011 : MCF/8
100 : MCF/16, 101 : MCF/32, 110 : MCF/64, 111 : MCF/128
Strobe Enable
Clock Division
Sensor Control C [SCTRC : 03h : 01h]
7
6
5
4
3
2
1
0
Bayer
Output
Enable
Single
Shot
Mode
Black
Level
Average
Output
0
HSYNC in
VBLANK
reserved
reserved
Black
Level
Data
Enable
0
Black
Level
Compens
ation
1
0
0
0
0
0
Bayer Output Enable
Single Shot Mode
Black Level Average
Output
More information is available on Bayer Data Format section.
With this register set to High, single video image is streamed out.
This bit enable R/G/B Active Offset registers[24h-26h] to represent black
level average value, instead of updated active offset values
VBLANK is equivalent to VSYNC, and HSYNC is the inversion of
HBLANK, and this bit controls whether HSYNC is active or not when
VBLANK unit is LCF.
HSYNC in VBLANK
VSYNC
(VBLANK)
HSYNC
Black Level Data
Enable
Black Level
Compensation
HSYNC is generated for light-shielded pixels in 4 lines.
Black level average values of light-shielded pixels are compensated when
active image data is produced.
Row Start Address Upper [RSAU : 08h : 00h]
7
6
5
4
3
2
1
0
Reserved
Row Start Address
Upper
0
R0
R0
R0
R0
R0
R0
0
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