- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371906 > HV7161SPA2 (Electronic Theatre Controls, Inc.) CMOS Image Sensor with Image Signal Processing PDF資料下載
參數(shù)資料
| 型號： | HV7161SPA2 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | CMOS Image Sensor with Image Signal Processing |
| 中文描述： | 的CMOS圖像傳感器和圖像信號處理 |
| 文件頁數(shù)： | 68/72頁 |
| 文件大?。?/td> | 2023K |
| 代理商： | HV7161SPA2 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁當(dāng)前第68頁第69頁第70頁第71頁第72頁
Confidential
HV7161SPA2
CMOS Image Sensor
With Image Signal Processing
DC Operating Conditions
This document has a general product description and is subject to change without notice.
MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described
and no patent licenses are implied.
- 68 -
2005 MagnaChip Semiconductor Ltd.
Symbol
Parameter
Units
Min.
Typ.
Max.
Load[pF]
Vdd:ph
I/O and pixel block supply
voltage
Internal analog an digital
operation supply voltage
Input voltage logic "1"
Volt
2.3
2.5 to 2.8
2.9
Vdd:p
Volt
1.6
1.8
2.0
Vih
Volt
2.0
30[pF]
Vil
Input voltage logic "0"
Volt
0.8
30[pF]
Voh
Output voltage logic "1"
Volt
2.4
30[pF]
Vol
Output voltage logic "0"
Volt
0.4
30[pF]
Iih
Input High Current
uA
-10
10
30[pF]
Iil
Input Low Current
uA
-10
10
30[pF]
Ta
Ambient operating temperature
°
C
-10
25
50
AC Operating Conditions
Symbol
Parameter
Max Operation Frequency
Units
Notes
MCLK
Main clock frequency
I
2
C clock frequency
21
MHz
1,2
SCK
1. MCLK may be divided by internal clock division logic for easy integration with high speed
video codec system.
2. Frame Rate : 15 frames/sec at 21Mhz, HBLANK = 208, VBLANK = 8
3. SCK is driven by host processor. For the detail serial bus timing, refer to I2C chip
interface section
Output AC Characteristics
All output timing delays are measured with output load 30[pF]. Output delay includes the internal
clock path delay and output driving delay that changes in respect to the output load, the operating
environment, and a board design. Due to the variable valid time delay of the output, video output
signals Y[7:0], C[7:0], HSYNC, and VSYNC may be latched in the negative edge of VCLK for the
stable data transfer between the image sensor and video codec.
400
KHz
3
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HVC145 | Silicon Epitaxial Planar Pin Diode for Antenna Switching |
| HVC190 | Silicon Epitaxial Planar PIN Diode for High Frequency Attenuator |
| HVC380B | Variable Capacitance Diode for VCO |
| HVC381B | Variable Capacitance Diode for VCO |
| HVD144A | Silicon Epitaxial Trench Pin Diode for Antenna Switching |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HV71SM-142 | 制造商:APITECH 制造商全稱:APITECH 功能描述:Voltage Controlled Oscillator |
| HV71SM-32 | 制造商:SPECTRUM 制造商全稱:Spectrum Microwave, Inc. 功能描述:Voltage Controlled Oscillator |
| HV71T-14 | 制造商:SPECTRUM 制造商全稱:Spectrum Microwave, Inc. 功能描述:Voltage Controlled Oscillator |
| HV71T-3 | 制造商:SPECTRUM 制造商全稱:Spectrum Microwave, Inc. 功能描述:Voltage Controlled Oscillator |
| HV7224 | 制造商:SUPERTEX 制造商全稱:SUPERTEX 功能描述:40-Channel Symmetric Row Driver |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。