HT49C10
12
September 28, 1999
Labels
Bits
Function
C
0
Cissetiftheoperationresultsinacarryduringanadditionoperationorifabor-
row does not take place during a subtraction operation; otherwise C is cleared. C
is also affected by a rotate through carry instruction.
AC
1
ACissetiftheoperationresultsinacarryoutofthelownibblesinadditionorno
borrow from the high nibble into the low nibble in subtraction; otherwise AC is
cleared.
Z
2
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is
cleared.
OV
3
OV is set if the operation results in a carry into the highest-order bit but not a
carry out of the highest-order bit, or vice versa; otherwise OV is cleared.
PD
4
PD is cleared by either a system power-up or executing the CLR WDT instruc-
tion. PD is set by executing the HALT instruction.
TO
5
TO is cleared by a system power-up or executing the CLR WDT or HALT in-
struction. TO is set by a WDT time-out.
6, 7
Undefined, read as 0
STATUS register
ister does not alter the TO or PD flags. Opera-
tions related to the status register, however, may
yield different results from those intended. The
TO and PD flags can only be changed by a watch-
dogtimeroverflow,chippower-up,orclearingthe
watchdog timer and executing the HALT in-
struction. The Z, OV, AC, and C flags reflect the
status of the latest operations.
On entering the interrupt sequence or execut-
ing the subroutine call, the status register will
not be pushed onto the stack automatically. If
the contents of the status is important, and if
the subroutine is likely to corrupt the status
register, precautions should be taken to save it
properly.
Interrupts
The HT49C10 provides two external interrupts,
an internal timer/event counter interrupt, an
internal time base interrupt, and an internal
real time clock interrupt. The interrupt control
register 0 (INTC0;0BH) and interrupt control
register 1 (INTC1;1EH) both contain the inter-
rupt control bits that are used to set the en-
able/disablestatusandinterruptrequestflags.
Once an interrupt subroutine is serviced, other
interrupts are all blocked (by clearing the EMI
bit). This scheme may prevent any further in-
terrupt nesting. Other interrupt requests may
take place during this interval, but only the in-
terrupt request flag will be recorded. If a cer-
tain interrupt requires servicing within the
service routine, the programmer may set the
EMI bit and the corresponding bit of INTC0 or of
INTC1 in order to allow interrupt nesting. Once
the stack is full, the interrupt request will not be
acknowledged, even if the related interrupt is en-
abled, until the SP is decremented. If immediate
service is desired, the stack should be prevented
from becoming full.
All these interrupts have the wake-up capability.
When an interrupt is serviced, a control trans-
fer occurs by pushing the PC onto the stack, fol-
lowed by a branch to subroutines at the
specified locations in the ROM. Only the PC is
pushed onto the stack. If the contents of the reg-
ister or of the status register (STATUS) is al-
tered by the interrupt service program which
corrupts the desired control sequence, the con-
tents should be saved first.
External interrupts are triggered by a high to
low transition of INT0 or INT1, and the related