參數(shù)資料
型號: HN29W6484DH08TE
廠商: Hitachi,Ltd.
英文描述: Controller for AND Flash Memory(AND型閃速存儲器控制器)
中文描述: 控制器及快閃記憶體(及型閃速存儲器控制器)
文件頁數(shù): 7/74頁
文件大?。?/td> 251K
代理商: HN29W6484DH08TE
HN29W6484DH08TE-1
7
Host Interface Pin Explanation
Signal name
Direction Pin No.
Description
A10 to A0
(PC Card Memory mode)
I
100, 107, 108,
109, 110, 118,
119, 120, 1, 6, 7
Address bus is A10 to A0. A10 is MSB and A0 is
LSB.
A10 to A0
(PC Card I/O mode)
A2 to A0
(True IDE mode)
1, 6, 7
Address bus is A10 to A0. Only A2 to A0 are used,
A10 to A3 should be grounded by the host.
BVD1
(PC Card Memory mode)
I/O
5
BVD1 outputs the battery voltage status in the card.
This output line is constantly driven to a high state
since a battery is not required for this product.
-STSCHG
(PC Card I/O mode)
-STSCHG is used for changing the status of
Configuration and status register in attribute area.
-PDIAG
(True IDE mode)
-PDIAG is the Pass Diagnostic signal in Master/Slave
handshake protocol.
BVD2
(PC Card Memory mode)
I/O
4
BVD2 outputs the battery voltage status in the card.
This output line is constantly driven to a high state
since a battery is not required for this product.
-SPKR
(PC Card I/O mode)
-SPKR outputs speaker signals. This output line is
constantly driven to a high state since this product
does not support the audio function.
-DASP
(True IDE mode)
-DASP is the Disk Active/Slave Present signal in the
Master/Slave handshake protocol.
-CE1, -CE2
(PC Card Memory mode)
Card Enable
I
99, 103
-CE1 and -CE2 are low active card select signals.
Byte/Word/Odd byte mode are defined by combination
of -CE1, -CE2 and A0.
-CE1, -CE2
(PC Card I/O mode)
Card Enable
-CE1, -CE2
(True IDE mode)
-CE2 is used for select the Alternate Status Register
and the Device Control Register while -CE1 is the chip
select for the other task file registers.
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