參數(shù)資料
型號: HN29W6484DH08TE
廠商: Hitachi,Ltd.
英文描述: Controller for AND Flash Memory(AND型閃速存儲器控制器)
中文描述: 控制器及快閃記憶體(及型閃速存儲器控制器)
文件頁數(shù): 15/74頁
文件大?。?/td> 251K
代理商: HN29W6484DH08TE
HN29W6484DH08TE-1
15
2. Task File register access specifications
There are two cases of Task File register mapping, one is mapped I/O address area, the other is mapped Memory address
area. Each case of Task File register read and write operations are executed under the condition as follows. That area can
be accessed by Byte/Word/Odd Byte mode which are defined by PC card standard specifications.
(1) I/O address map
Task File Register Read Access Mode (1)
Mode
-REG
-CE2
-CE1
A0
-IORD -IOWR -OE
-WE
D8 to D15 D0 to D7
Standby mode
×
H
H
×
×
×
×
×
High-Z
High-Z
Byte access (8-bit)
L
H
L
L
L
H
H
H
High-Z
even byte
L
H
L
H
L
H
H
H
High-Z
odd byte
Word access (16-bit)
L
L
L
×
×
L
H
H
H
odd byte
even byte
Odd byte access (8-bit)
Note:
×
: L or H
L
L
H
L
H
H
H
odd byte
High-Z
Task File Register Write Access Mode (1)
Mode
-REG
-CE2
-CE1
A0
-IORD -IOWR -OE
-WE
D8 to D15 D0 to D7
Standby mode
×
H
H
×
×
×
×
×
Don’t care Don’t care
Byte access (8-bit)
L
H
L
L
H
L
H
H
Don’t care even byte
L
H
L
H
H
L
H
H
Don’t care odd byte
Word access (16-bit)
L
L
L
×
×
H
L
H
H
odd byte
even byte
Odd byte access (8-bit)
Note:
×
: L or H
L
L
H
H
L
H
H
odd byte
Don’t care
Task File Register Access Timing Example (1)
Dout
A0 to A10
-REG
-CE2/-CE1
-IORD
- IOWR
D0 to D15
read cycle
write cycle
Din
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