參數(shù)資料
型號: HN29W6484DH08TE
廠商: Hitachi,Ltd.
英文描述: Controller for AND Flash Memory(AND型閃速存儲器控制器)
中文描述: 控制器及快閃記憶體(及型閃速存儲器控制器)
文件頁數(shù): 42/74頁
文件大?。?/td> 251K
代理商: HN29W6484DH08TE
HN29W6484DH08TE-1
42
Note:
FR: Feature register
SC: Sector Count register
SN: Sector Number register
CY: Cylinder register
DR: DRV bit of Drive Head register
HD: Head Number of Drive Head register
LBA: Logical Block Address Mode Supported
Y: The register contains a valid parameter for this command.
N: The register does not contain a valid parameter for this command.
12. Device control register:
This register is write only register, and it is used for controlling the card
interrupt request and issuing an ATA soft reset to the card.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
×
×
×
×
1
SRST
nIEN
0
bit
Name
Function
7 to 4
×
don't care
3
1
This bit is set to "1".
2
SRST (Software ReSeT)
This bit is set to "1" in order to force the card to perform Task File
Reset operation. This does not change the Card Configuration
registers as a Hardware Reset does. The card remains in Reset
until this bit is reset to "0".
1
nIEN (Interrupt ENable)
This bit is used for enabling -IREQ. When this bit is set to "0", -IREQ
is enabled. When this bit is set to "1", -IREQ is disabled.
0
0
This bit is set to "0".
13. Drive Address register:
This register is read only register, and it is used for confirming the drive status.
This register is provides for compatibility with the AT disk drive interface. It is recommended that this
register is not mapped into the host’s I/O space because of potential conflicts on bit7.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
×
nWTG
nHS3
nHS2
nHS1
nHS0
nDS1
nDS0
bit
Name
Function
7
×
This bit is unknown
6
nWTG (WriTing Gate)
This bit is unknown
5 to 2 nHS3-0 (Head Select3-0)
These bits is the negative value of Head Select bits (bit 3 to 0) in
Drive/Head register.
1
nDS1 (Idrive Select1)
This bit is unknown
0
nDS0 (Idrive Select0)
This bit is unknown
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