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參數(shù)資料
| 型號： | HFA3863 |
| 廠商： | Intersil Corporation |
| 元件分類： | 基帶處理器 |
| 英文描述： | Direct Sequence Spread Spectrum Baseband Processor(直接序列擴(kuò)譜基帶處理器) |
| 中文描述： | 直接序列擴(kuò)頻基帶處理器（直接序列擴(kuò)譜基帶處理器） |
| 文件頁數(shù)： | 36/39頁 |
| 文件大?。?/td> | 305K |
| 代理商： | HFA3863 |
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4-36
TX_CLK to TX_PE Inactive (11Mbps)
t
PEH
t
RI
t
ME
t
RLP
t
RCP
t
RCD
t
RDD
t
RD1
t
RD1
t
RDS
t
REH
t
REH
t
REH
t
REH
t
RD2
t
RD3
0
65
ns (Notes 8, 19)
TX_RDY Inactive to Last Chip of MPDU Out
-20
800
ns
TXD Modulation Extension
2
-
μ
s (Notes 8, 12)
RX_PE Inactive Width
70
-
ns (Notes 8, 13)
RX_CLK Period (11Mbps Mode)
90
-
ns
RX_CLK Width Hi or Low (11Mbps Mode)
44
-
ns
RX_CLK to RXD
25
60
ns
MD_RDY to 1st RX_CLK
940
-
ns (Notes 8, 16)
RXD to 1st RX_CLK
940
-
ns
Setup RXD to RX_CLK
31
-
ns
RX_CLK to RX_PE Inactive (1Mbps)
0
925
ns (Notes 8, 14)
RX_CLK to RX_PE Inactive (2Mbps)
0
380
ns (Notes 8, 14)
RX_CLK to RX_PE Inactive (5.5Mbps)
0
140
ns (Notes 8, 14)
RX_CLK to RX_PE Inactive (11Mbps)
0
50
ns (Notes 8, 14)
RX_PE inactive to MD_RDY Inactive
5
30
ns (Note 15)
Last Chip of SFD in to MD_RDY Active
2.77
2.86
μ
s (Notes 8, 16)
RX Delay
2.77
2.86
μ
s (Notes 8, 17)
RESET Width Active
t
RPW
t
CCA
t
CCA
t
SCP
t
SCW
t
SCS
t
SCH
t
SCD
t
SCED
t
D2
50
-
ns (Notes 8, 18)
RX_PE to CCA Valid
-
16
μ
s (Note 8)
RX_PE to RSSI Valid
-
16
μ
s (Note 8)
SCLK Clock Period
90
-
ns
SCLK Width Hi or Low
20
-
ns
Setup to SCLK + Edge (SD, SDI, R/W, CS)
30
-
ns
Hold Time from SCLK + Edge (SD, SDI, R/W, CS)
0
-
ns
SD Out Delay from SCLK + Edge
-
30
ns
SD Out Enable/Disable from R/W
-
15
ns (Note 8)
TEST 0-7, CCA, ANTSEL, TEST_CK from MCLK
-
40
ns
NOTES:
7. AC tests performed with C
L
= 40pF, I
OL
= 2mA, and I
OH
= -1mA. Input reference level all inputs V
CC
/2. Test V
IH
= V
CC
, V
IL
= 0V;
V
OH
= V
OL
= V
CC
/2.
8. Not tested, but characterized at initial design and at major process/design changes.
9. Measured from V
IL
to V
IH
.
10. I
OUT
/Q
OUT
are modulated before first valid chip of preamble is output to provide ramp up time for RF/IF circuits.
11. TX_PE must be inactive before going active to generate a new packet.
12. I
OUT
/Q
OUT
are modulated after last chip of valid data to provide ramp down time for RF/IF circuits.
13. RX_PE must be inactive at least 3 MCLKs before going active to start a new CCA or acquisition.
14. RX_PE active to inactive delay to prevent next RX_CLK.
15. Assumes RX_PE inactive after last RX_CLK.
16. MD_RDY programmed to go active after SFD detect. (Measured from I
IN
, Q
IN
.)
17. MD_RDY programmed to go active at MPDU start. Measured from first chip of first MPDU symbol at I
IN
, Q
IN
to MD_RDY active.
18. Minimum time to ensure Reset. RESET must be followed by an RX_PE pulse to ensure proper operation. This pulse should not be used for first
receive or acquisition.
19. Delay from TXCLK to inactive edge of TXPE to prevent next TXCLK. Because TXPE asynchronously stops TXCLK, TXPE going inactive within
40ns of TXCLK will cause TXCLK minimum hi time to be less than 40ns.
AC Electrical Specifications
V
CC
= 3.0V to 3.3V
±
10%, T
A
= -40
o
C to 85
o
C (Note 8)
(Continued)
PARAMETER
SYMBOL
MCLK = 44MHz
UNITS
MIN
MAX
HFA3863
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HFA3863IN | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
| HFA3863IN96 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
| HFA3925 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:null2.4GHz - 2.5GHz 250mW Power Amplifier |
| HFA3925IA | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述: |
| HFA3925IA1K | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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