參數(shù)資料
型號(hào)： HFA3863
廠商： Intersil Corporation
元件分類： 基帶處理器
英文描述： Direct Sequence Spread Spectrum Baseband Processor(直接序列擴(kuò)譜基帶處理器)
中文描述： 直接序列擴(kuò)頻基帶處理器（直接序列擴(kuò)譜基帶處理器）
文件頁數(shù)： 32/39頁
文件大?。?/td> 305K
代理商： HFA3863
4-32
CONFIGURATION REGISTER ADDRESS 41 (52h) R/W PREAMBLE/HEADER LEAD COEFFICIENT
Bit 7:6
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bit 5:0
Preamble Lead Coefficient (0-4 range) (000000 - 100000).
CONFIGURATION REGISTER ADDRESS 42 (54h) R/W PREAMBLE/HEADER LAG COEFFICIENT
Bit 7:6
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bit 5:0
Preamble Lag Coefficient (0-4 range) (000000 - 100000).
CONFIGURATION REGISTER ADDRESS 43 (56h) R/W MPDU LEAD COEFFICIENT
Bit 7:6
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bit 5:0
Header Lead Coefficient (0-4 range) (000000 - 100000).
CONFIGURATION REGISTER ADDRESS 44 (58h) R/W MPDU LAG COEFFICIENT
Bit 7:6
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bit 5:0
Header Lag Coefficient (0-4 range) (000000 - 100000).
CONFIGURATION REGISTER ADDRESS 45 (5Ah) R/W FALSE ALARM RATE OF SQ1
Bits 7:0
False alarm rate of SQ1. Enable/disable with CR47 bit 7.
Rate = N*32/2^16. For example 01h = 0.05% False Alarm Rate (FAR) and 10h = 0.78% FAR.
CONFIGURATION REGISTER ADDRESS 46 (5Ch) R/W ACQUISITION TIMELINE
Bit 7
Long Preamble timeline disable.
0 = enable long preamble timeline processing.
1 = disable long preamble timeline processing (process all preambles as if short).
Bit 6
Long Preamble timeline diversity metric selection.
0 = H factors.
1 = RSSI.
Bits 5:0
SQ1 threshold #2, range 0 to 7.875. (000.00 - 111.111).
Used for verify cycle.
CONFIGURATION REGISTER ADDRESS 47 (5Eh) R/W ACQUISITION THRESHOLDS
Bit 7
Disable False alarm Rate Processing.
0 = Enable, SQ1 #1 threshold is adjusted in real time by FAR logic.
1 = Disable, SQ1 #1 threshold is set to value of CR 47 (5:0).
Bit 6
ED and SQ2 control for acquisition.
0 = SQ1.
1 = ED and SQ1.
Bits 5:0
SQ1 threshold #1, range 0 to 7.875. (000.00 - 111.111).
Used for initial detect and initial setting for FAR.
CONFIGURATION REGISTER ADDRESS 48 (60h) R/W SCRAMBLER SEED, LONG PREAMBLE
Bit 7
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bit 6:0
Scrambler seed for long preamble. Bit 3 of CR5 selects CR48 or CR49.
CONFIGURATION REGISTER ADDRESS 49 (62h) R/W SCRAMBLER SEED AND READ ONLY REGISTER MUX CONTROL
Bit 7
Read only register mux control.
0 = READ ONLY registers read ‘b’ value.
1 = READ ONLY registers read ‘a(chǎn)’ value.
Bits 6:0
Scrambler seed for short preamble. Bit 3 of CR5 selects CR48 or CR49.
CONFIGURATION REGISTER ADDRESS 50 (64h) R TEST BUS READ
Bit 7:0
a&b: reads value on test bus.
HFA3863
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HFA3863IN 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor
HFA3863IN96 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor
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