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參數(shù)資料
| 型號(hào)： | HFA3863 |
| 廠商： | Intersil Corporation |
| 元件分類： | 基帶處理器 |
| 英文描述： | Direct Sequence Spread Spectrum Baseband Processor(直接序列擴(kuò)譜基帶處理器) |
| 中文描述： | 直接序列擴(kuò)頻基帶處理器（直接序列擴(kuò)譜基帶處理器） |
| 文件頁(yè)數(shù)： | 26/39頁(yè) |
| 文件大小： | 305K |
| 代理商： | HFA3863 |
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4-26
CONFIGURATION REGISTER 10 ADDRESS (14h) R/W RX CONFIGURE
Bit 7
AGC freeze during packet.
0 = Disable (do not disable unless MAC can handle baseband processor aborting during MPDU reception).
1 = Enable.
Bit 6
CIR estimate/ Dot product clock control.
0 = on during acquisition.
1 = only on after detect.
Bit 5
ISI equalizer control.
0 = enable equalizer.
1 = disable equalizer.
Bit 4
ICI equalizer control.
0 = enable equalizer.
1 = disable equalizer.
Bit 3
MD_RDY control.
0 = After CRC16.
1 = After SFD.
Bit 2
Slot diversity mode control.
0 = disabled, Antenna diversity on for entire slot.
1 = enabled, Antenna diversity disabled for last half of slot - saves acquisition time, use in system where nodes are slot aligned.
Bit 1
Antenna choice for Receiver when single antenna acquisition is selected.
0 = Antenna select pin low.
1 = Antenna select pin high.
Bit 0
Single or dual antenna acquire.
0 = dual antenna for diversity acquisition.
1 = single antenna.
CONFIGURATION REGISTER 11 ADDRESS (16h) R/W RX-TX CONFIGURE
Bit 7
Continuous internal RX 22 and 44MHz clocks; (Only Reset active will stop).
0 = normal.
1 = continuous, overrides CR10 bit 6.
Bit 6
A/D input coupling.
0 = DC.
1 = AC (external bias network required).
Bit 5
Reserved.
Bit 4
Short Preamble test mode.
0 = use CR3 for short preamble.
1 = run TX and RX short preamble using preamble length in CR4.
Bit 3
CCA mode.
0 = normal (raw) mode CCA. CCA will immediately respond to changes in ED, CS1, and SQ1 as configured.
1 = Sampled mode CCA. CCA will update once per slot (20
μ
s), will be valid at 18.7
μ
s or 15.8
μ
s as determined by CR9 bit 7.
Bits 2:0
Precursor value in CIR estimate.
CONFIGURATION REGISTER 12 ADDRESS (18h) R/W A/D TEST MODES 1
Bit 7
All DAC and A/D clock source control.
0 = normal internal clocks.
1 = clock via SDI pin.
Bit 6
TX DAC clock.
0 = enable.
1 = disable.
Bit 5
RX DAC clock.
0 = enable.
1 = disable.
Bit 4
I DAC clock.
0 = enable.
1 = disable.
HFA3863
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HFA3863IN | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
| HFA3863IN96 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
| HFA3925 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:null2.4GHz - 2.5GHz 250mW Power Amplifier |
| HFA3925IA | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述: |
| HFA3925IA1K | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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