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參數(shù)資料
| 型號： | HFA3863 |
| 廠商： | Intersil Corporation |
| 元件分類： | 基帶處理器 |
| 英文描述： | Direct Sequence Spread Spectrum Baseband Processor(直接序列擴(kuò)譜基帶處理器) |
| 中文描述： | 直接序列擴(kuò)頻基帶處理器（直接序列擴(kuò)譜基帶處理器） |
| 文件頁數(shù)： | 17/39頁 |
| 文件大?。?/td> | 305K |
| 代理商： | HFA3863 |
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4-17
correlators, one for the I and one for the Q Channel. The
same Barker sequence is always used for both I and Q
correlators.
These correlators are time invariant matched filters otherwise
known as parallel correlators. They use one sample per chip for
correlation although two samples per chip are processed. The
correlator despreads the samples from the chip rate back to the
original symbol rate giving 10.4dB processing gain for 11 chips
per symbol. While despreading the desired signal, the
correlator spreads the energy of any non correlating interfering
signal.
The second form of correlator is the parallel correlator bank
used for detection of the CCK modulation. For the CCK
modes, the 64 wide bank of parallel correlators is
implemented with a Fast Walsh Transform to correlate the 4
or 64 code possibilities. This greatly simplifies the circuitry of
the correlation function. It is followed by a biggest picker
which finds the biggest of 4 or 64 correlator outputs
depending on the rate. This is translated into 2 or 6 data bits.
The detected output is then processed through the
differential phase decoder to demodulate the last two bits of
the symbol.
Data Demodulation and Tracking
Description (DBPSK and DQPSK Modes)
The signal is demodulated from the correlation peaks
tracked by the symbol timing loop (bit sync) as shown in
Figure 12. The frequency and phase of the signal is
corrected using the NCO that is driven by the phase locked
loop. Averaging the phase errors over 10 symbols gives the
necessary frequency information for seeding the NCO
operation.
Data Decoder and Descrambler
Description
The data decoder that implements the desired DQPSK
coding/decoding as shown in Table 8. The data is formed
into pairs of bits called dibits. The left bit of the pair is the first
in time. This coding scheme results from differential coding
of the dibits. Vector rotation is counterclockwise for a positive
phase shift, but can be reversed with bit 7 or 6 of CR 1.
For DBPSK, the decoding is simple differential decoding.
The data scrambler and de-scrambler are self synchronizing
circuits. They consist of a 7-bit shift register with feedback of
some of the taps of the register. The scrambler is designed
to ensure smearing of the discrete spectrum lines produced
by the PN code.
One thing to keep in mind is that both the differential decoding
and the descrambling cause error extension or burst errors.
This is due to two properties of the processing. First, the
differential decoding process causes errors to occur on pairs of
symbols. When a symbol’s phase is in error, the next symbol
will also be decoded wrong since the data is encoded in the
change in phase from one symbol to the next. Thus, two errors
are made on two successive symbols. Therefore up to 4 bits
may be wrong although on the average only 2 are. In QPSK
mode, these may occur next to one another or separated by up
to 2 bits. In the CCK mode, when a symbol decision error is
made, up to 6 bits may be in error although on average only 3
bits will be in error. Secondly, when the bits are processed by
the descrambler, these errors are further extended. The
descrambler is a 7-bit shift register with two taps exclusive or’ed
with the bit stream. Thus, each error is extended by a factor of
three. Multiple errors can be spaced the same as the tap
spacing, so they can be canceled in the descrambler. In this
case, two wrongs do make a right. Given all that, if a single
error is made the whole packet is discarded anyway, so the
error extension property has no effect on the packet error rate.
It should be taken into account if a forward error correction
scheme is contemplated.
Descrambling is self synchronizing and is done by a
polynomial division using a prescribed polynomial. A shift
register holds the last quotient and the output is the exclusive-
or of the data and the sum of taps in the shift register.
TABLE 8. DQPSK DATA DECODER
PHASE SHIFT
DIBIT PATTERN (D0, D1)
D0 IS FIRST IN TIME
0
00
+90
01
+180
11
-90
10
T0 + 1 SYMBOL CORRELATOR
OUTPUT REPEATS
CORRELATION
PEAK
T0 + 2 SYMBOLS
T0
SAMPLES
AT 2X CHIP
RATE
EARLY
ON-TIME
LATE
CORRELATION TIME
FIGURE 12. CORRELATION PROCESS
CORRELATOR OUTPUT IS THE RESULT OF CORRELATING
THE PN SEQUENCE WITH THE RECEIVED SIGNAL
HFA3863
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相關(guān)代理商/技術(shù)參數(shù) |
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| HFA3863IN | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
| HFA3863IN96 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
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