參數(shù)資料
型號(hào): HD66732
廠商: Hitachi,Ltd.
英文描述: Graphics Liquid Crystal Display Controller/Driver Supporting JIS Level-1 and Level-2 Kanji ROM(圖形LCD控制器/驅(qū)動(dòng)器)
中文描述: 圖形液晶顯示控制器/驅(qū)動(dòng)器支持日標(biāo)級(jí)- 1和第2級(jí)漢字光盤(圖形液晶顯示控制器/驅(qū)動(dòng)器)
文件頁數(shù): 65/133頁
文件大?。?/td> 2608K
代理商: HD66732
HD66732
65
a) Basic Data-transfer Timing through Clock-synchronized Serial Bus Interface
Start byte
Instruction, RAM data, key-scanned data
SCL
(Input)
CS*
(Input)
Transfer start
Transfer end
Start byte
RS = 1, R/W = 0
SCL
(Input)
b) Consecutive RAM Data-transfer Timing
1 2 3 4 5 6 7 8
9 101112 131415 16
17 1819
RAM write data 1
RAM write data 2
20 212223 24
252627 282930 3132
RAM write data 3
Start
End
CS*
(Input)
SDA
(Input/
output)
SDA
(Input/
output)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DB7 DB6 DB5 DB4
R/W
Device ID code
ID
RS
DB3 DB2 DB1 DB0
MSB
RS
"1"
R/W
"1"
"0"
"1"
"0"
LSB
Start byte
RS = 1, R/W = 1
SCL
(Input)
c) RAM Data Read-transfer Timing
1 2 3 4 5 6 7 8
9 101112 131415 16
17 1819
Dummy read 1
Dummy read 2
20 212223 24
252627 282930 3132
RAM data read 1
Start
End
CS*
(Input)
SDA
(Input/
output)
Note: The RAM address setting registers (RC and RD) select the write RAM or set the write-start RAM address.
Note: Two bytes of the RAM read data after the start byte are invalid. The HD66732 starts to read the correct RAM
data from the third byte.
Figure 24 Clock-synchronized Serial Interface Timing Sequence
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