參數(shù)資料
型號(hào)： HD66732
廠商： Hitachi,Ltd.
英文描述： Graphics Liquid Crystal Display Controller/Driver Supporting JIS Level-1 and Level-2 Kanji ROM(圖形LCD控制器/驅(qū)動(dòng)器)
中文描述： 圖形液晶顯示控制器/驅(qū)動(dòng)器支持日標(biāo)級(jí)- 1和第2級(jí)漢字光盤(pán)（圖形液晶顯示控制器/驅(qū)動(dòng)器）
文件頁(yè)數(shù)： 55/133頁(yè)
文件大小： 2608K
代理商： HD66732
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HD66732
55
Table 37
AD Bits and CGRAM Setting (GR = 0)
RM1/0
AD9–AD0
CGRAM (1) Setting in the Character Mode (GR = 0)
10
"000"H–"077"H
Upper font pattern of CGRAM characters (1) to (10)
10
"100"H–"177"H
Lower font pattern of CGRAM characters (1) to (10)
10
"200"H–"277"H
Upper font pattern of CGRAM characters (11) to (20)
10
"300"H–"377"H
Lower font pattern of CGRAM characters (11) to (20)
10
"400"H–"477"H
Upper font pattern of CGRAM characters (21) to (30)
10
"500"H–"577"H
Lower font pattern of CGRAM characters (21) to (30)
Table 38
AD Bits and CGRAM Setting (GR = 1)
RM1/0
AD10–AD0
CGRAM Setting in the Graphics Mode (GR = 1)
10
"000"H–"077"H
Bit map data for COM1 to COM8
10
"100"H–"177"H
Bit map data for COM9 to COM16
10
"200"H–"277"H
Bit map data for COM17 to COM24
10
"300"H–"377"H
Bit map data for COM25 to COM32
10
"400"H–"477"H
Bit map data for COM33 to COM40
10
"500"H–"577"H
Bit map data for COM41 to COM48
10
"600"H–"677"H
Bit map data for COM49 to COM52
Table 39
AD Bits and SEGRAM Setting
RM1/0
AD10–AD0
SEGRAM Setting
11
"000"H–"077"H
SEGRAM display data
RAM Data (RF)
WD7-0 :
Write 8-bit data to the DDRAM and CGRAM, and lower 2-bit data to the SEGRAM. The
DDRAM/CGRAM/SEGRAM is selected by the previous specification of the RM 1/0 bit. After a write, the
address is automatically incremented or decremented by 1 according to the I/D bit setting in the entry mode
set instruction. During the sleep and standby modes, the DDRAM, CGRAM, or SEGRAM cannot be
accessed.
RD7-0 :
Read 8-bit data from the DDRAM, CGRAM or SEGRAM. The DDRAM, CGRAM, or SEGRAM
is selected by the previous specification of the RM 1/0 bit. In the parallel bus interface mode, the first-byte
data read will be invalid immediately after the RAM address set, and the consecutive second-byte data will
be read normally. In the serial interface mode, two bytes will be invalid immediately after the start byte,
and the consecutive third-byte data will be read normally. For details, see the Serial Data Transfer section.
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