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參數(shù)資料
| 型號： | HD66732 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | Graphics Liquid Crystal Display Controller/Driver Supporting JIS Level-1 and Level-2 Kanji ROM(圖形LCD控制器/驅(qū)動器) |
| 中文描述： | 圖形液晶顯示控制器/驅(qū)動器支持日標級- 1和第2級漢字光盤（圖形液晶顯示控制器/驅(qū)動器） |
| 文件頁數(shù)： | 15/133頁 |
| 文件大?。?/td> | 2608K |
| 代理商： | HD66732 |
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HD66732
15
Block Function Description
System Interface
The HD66732 has five types of system interfaces, and a clock-synchronized serial interface, a 68-system 4-
bit/8-bit bus, and a 80-system 4-bit/8-bit bus. The interface mode is selected by the IM2-0 pins. The key
scan of the HD66732 is not available for the 4-bit/8-bit bus interface. Instead, use the clock-synchronized
serial interface.
The HD66732 has five 8-bit registers: an index register (IR), a status register (SR), control registers, a
RAM address register, and a RAM data register.
The IR specifies the index address of the register to be accessed. The SR reads the key scan data in the
serial interface mode, and the internal states in the bus interface mode. Control registers (CNRs) set
instructions such as clear display or display control. The RAM address register and RAM data register
store the addresses or data of the display data RAM (DDRAM), character generator RAM (CGRAM), or
segment RAM (SEGRAM).
Data written into the RAM data register from the MPU is automatically written into the DDRAM,
CGRAM, or SEGRAM by internal operation. Data is read and temporarily latched in the RAM data
register when reading from the RAM, and the first read data is invalid and the second data is normal. After
reading, data in the DDRAM, CGRAM, or SEGRAM at the next address is sent to the RAM data register
for the next reading from the MPU.
Execution time for instructions, excluding clear display, is 0 clock cycles and instructions can be written in
succession.
Table 3
Register Selection by RS and R/W Bits
R/W Bits
RS Bits
Operations
0
0
Writes to the index register (IR)
1
0
Reads the status register (SR)
0
1
Writes to the control register, RAM address register, and RAM data register
1
1
Reads the RAM data register
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HD66740TB0 | 50/MDR/RECP/VERT PRS FIT/M2.6/SCW/30MIN |
| HD66740WTB0 | 112 x 80-dot Graphics LCD Controller/Driver |
| HD66751 | 128 x 128-dot Graphics LCD Controller/Driver with Four-grayscale Functions |
| HD66750TB0 | 122 x 32 pixel format, Compact LCD size |
| HD66750 | 128 x 128-dot Graphics LCD Controller/Driver with Four-grayscale Functions |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HD66735 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:HD66735 Procedure for setting Standby/Sleep/Display off mode. Technical Update/Device |
| HD66740 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| HD66740TB0 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:112 x 80-dot Graphics LCD Controller/Driver |
| HD66740WTB0 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:112 x 80-dot Graphics LCD Controller/Driver |
| HD66741 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:128 x 128-dot Graphics LCD Controller/Driver with Four-grayscale Functions |
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